Fabrication method of three-dimensional memory device

Patent metadata

Field	Value
Publication number	US-12507407-B2
Application number	US-202217977161-A
Country	US
Kind code	B2
Filing date	Oct 31, 2022
Priority date	Aug 31, 2021
Publication date	Dec 23, 2025
Grant date	Dec 23, 2025

Abstract

A method of fabricating a three-dimensional (3D) memory device includes forming a stack structure on a substrate, forming a channel structure, a dummy channel structure, and a gate line slit structure penetrating through the stack structure and extending into the substrate, removing the substrate to expose a first side of the stack structure, forming a protective layer covering an exposed portion of the channel structure on the first side of the stack structure, removing at least the exposed portion of the channel structure, and removing the protective layer after removing at least the exposed portion of the channel structure.

First claim

What is claimed is:

1 . A method of fabricating a three-dimensional (3D) memory device, comprising:
forming a stack structure on a substrate; forming a channel structure, a dummy channel structure, and a gate line slit structure penetrating through the stack structure and extending into the substrate; removing the substrate to expose a first side of the stack structure; forming a protective layer covering an exposed portion of the dummy channel structure on the first side of the stack structure; removing at least a portion of an exposed portion of the channel structure; and removing the protective layer after removing at least the portion of the exposed portion of the channel structure, wherein an etch rate of removing the protective layer is lower than that of removing the portion of the exposed portion of the channel structure.

2 . The method of claim 1 , wherein the channel structure comprises a channel layer and a functional layer; and removing at least the portion of the exposed portion of the channel structure comprises removing at least an exposed portion of the functional layer in at least the portion of the exposed portion of the channel structure.

3 . The method of claim 1 , wherein before removing at least the portion of the exposed portion of the channel structure, the protective layer covers the gate line slit structure.

4 . The method of claim 1 , wherein removing at least the portion of the exposed portion of the channel structure uses the protective layer as an etch block layer.

5 . The method of claim 1 , wherein
the gate line slit structure comprises a conductive layer and an insulating layer; a first portion of the insulating layer covers a side wall of the conductive layer; a second portion of the insulating layer is formed between the conductive layer and the substrate; and the method further comprises removing a part of the second portion of the insulating layer in a same process of removing at least the portion of the exposed portion of the channel structure.

6 . The method of claim 1 , wherein
the gate line slit structure comprises a conductive layer and an insulating layer; a first portion of the insulating layer covers a side wall of the conductive layer; a second portion of the insulating layer is formed between the conductive layer and the substrate; and removing at least the portion of the exposed portion of the channel structure comprises removing the second portion of the insulating layer in a same process of removing at least the portion of the exposed portion of the channel structure.

7 . The method of claim 1 , wherein forming the channel structure, the dummy channel structure and the gate line slit structure penetrating through the stack structure and extending into the substrate further comprises forming a high dielectric constant layer at least partially covering a sidewall of the gate line slit structure.

8 . The method of claim 2 , wherein
the functional layer comprises a charge barrier layer, a charge trapping layer, and a tunneling layer; and the method further comprises removing the protective layer after the charge barrier layer and the charge trapping layer in the exposed portion of the functional layer being removed.

9 . The method of claim 8 , further comprising removing the tunneling layer in the exposed portion of the channel structure to expose the channel layer after the protective layer being removed.

10 . The method of claim 2 , wherein
the functional layer comprises a charge barrier layer, a charge trapping layer, and a tunneling layer; and the method further comprises removing the protective layer after removing the charge barrier layer, the charge trapping layer, and the tunneling layer in the exposed portion of the channel structure to expose the channel layer.

11 . The method of claim 10 , further comprising forming a semiconductor layer in contact with an exposed portion of the channel layer on the first side.

12 . The method of claim 11 , further comprising: forming a doped region in the exposed portion of the channel layer that is proximate to the semiconductor layer using an ion implantation process and a laser annealing process.

13 . The method of claim 1 , wherein the protective layer comprises a photoresist layer.

14 . The method of claim 1 , further comprising forming a second semiconductor structure on a second side of the stack structure before removing the substrate to expose the first side of the stack structure.

15 . The method of claim 14 , wherein the second semiconductor structure comprises at least a peripheral device comprising metal oxide semiconductor field effect transistor (MOSFET), bipolar transistor (BJT), diode, resistor, inductors, capacitor, or any combinations thereof.

16 . The method of claim 14 , further comprising forming an interconnect layer coupled between the second semiconductor structure and a word line contact, wherein the word line contact is in contact with a gate conductive layer.

17 . The method of claim 1 , wherein forming the stack structure comprises:
forming alternating gate sacrificial layers and dielectric layers; and after forming the gate line slit structure, replacing the gate sacrificial layers with gate conductive layers.

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Zhang Kun

Classifications

• H10B43/40

  characterised by the peripheral circuit region · CPC title

• H10B43/35

  with cell select transistors, e.g. NAND · CPC title

• H10B43/50

  characterised by the boundary region between the core and peripheral circuit regions · CPC title

• H10B43/20 Primary

  characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels · CPC title