Audio D/A converter, and DSD signal D/A conversion method

Patent metadata

Field	Value
Publication number	US-12506493-B2
Application number	US-202418604786-A
Country	US
Kind code	B2
Filing date	Mar 14, 2024
Priority date	Mar 14, 2023
Publication date	Dec 23, 2025
Grant date	Dec 23, 2025

Abstract

An audio D/A converter for converting direct stream digital (DSD) data having a modulation rate m into an analog signal includes: an N-bit (N≥2) segment type D/A converter, a shift register configured to store M-bits (N≤MSN/m) of the DSD data; and a controller configured to supply an N-bit output code containing p 1s to the segment type D/A converter when the number of 1s stored in the shift register is p.

First claim

What is claimed is:

1 . An audio digital-to-analog (D/A) converter for converting direct stream digital (DSD) data having a modulation rate m into an analog signal, comprising:
an N-bit (N≤2) segment type D/A converter; a shift register configured to store M-bits (N<M≤N/m) of the DSD data; and a controller configured to supply an N-bit output code containing p 1s to the segment type D/A converter when the number of 1s stored in the shift register is p.

2 . The audio D/A converter of claim 1 , wherein m is 0.5, N is 16, and M is 32.

3 . The audio D/A converter of claim 1 , wherein the shift register includes M flip-flops connected in series.

4 . The audio D/A converter of claim 1 , wherein the shift register includes N flip-flops connected in series, and (M−N) flip-flops connected in series.

5 . The audio D/A converter of claim 2 , wherein the shift register includes a first flip-flop group including N flip-flops connected in series to receive the DSD data, and a second flip-flop group including N flip-flops connected in series to receive the DSD data.

6 . The audio D/A converter of claim 2 , wherein the shift register includes a first flip-flop group including N/2 flip-flops connected in series to receive the DSD data, a second flip-flop group including N/2 flip-flops connected in series to receive the DSD data, a third flip-flop group including N/2 flip-flops connected in series to receive the DSD data, and a fourth flip-flop group including N/2 flip-flops connected in series to receive the DSD data.

7 . The audio D/A converter of claim 6 , wherein in the shift register, at least one selected from the group of the first flip-flop group to the fourth flip-flop group is configured to receive delayed DSD data.

8 . An audio digital-to-analog (D/A) converter for converting direct stream digital (DSD) data having a modulation rate m into an analog signal, comprising:
an N-bit (N≤2) segment type D/A converter; a shift register configured to hold N bits of the DSD data; and a controller configured to supply an N-bit output code containing α<n (where o is a constant satisfying (1<α≤1/m) 1s to the segment type D/A converter when the number of 1s contained in the shift register is n.

9 . The audio D/A converter of claim 8 , wherein the controller includes a counter configured to acquire the number n of 1s contained in the shift register, a multiplier configured to multiply a binary code representing the number n by α, and an encoder configured to generate an N-bit output code containing p 1s when an output of the multiplier is p.

10 . The audio D/A converter of claim 9 , wherein when α is 2 k (where k is a natural number), the multiplier is a bit shifter configured to bit-shift the binary code representing the number n by k bits to the left.

11 . The audio D/A converter of claim 8 , wherein the shift register is configured to hold N consecutive bits of the DSD data.

12 . The audio D/A converter of claim 8 , wherein the shift register includes a first flip-flop group configured to hold N/2 consecutive bits of the DSD data, and a second flip-flop group configured to hold N/2 consecutive bits of the DSD data.

13 . The audio D/A converter of claim 1 , which is monolithically integrated on one semiconductor substrate.

14 . A method of converting direct stream digital (DSD) data having a modulation rate m into an analog signal, comprising:
counting a number p of 1s contained in M consecutive bits (N<M≤N/m) of the DSD data; generating an N-bit output code containing p 1s; and converting the N-bit output code into the analog signal by an N-bit segment type D/A converter.

Assignees

• Rohm Co Ltd

Inventors

• Yamagami Shinji

Classifications

• G06F3/162

  Interface to dedicated audio devices, e.g. audio drivers, interface to CODECs · CPC title

• H03M1/80

  using weighted impedances (H03M1/76 takes precedence) · CPC title

• H03M1/66 Primary

  Digital/analogue converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title

• H03M1/747 Primary

  with equal currents which are switched by unary decoded digital signals · CPC title