Step down power converter with pre-dropout control

Patent metadata

Field	Value
Publication number	US-12506409-B2
Application number	US-202318396104-A
Country	US
Kind code	B2
Filing date	Dec 26, 2023
Priority date	Dec 26, 2023
Publication date	Dec 23, 2025
Grant date	Dec 23, 2025

Abstract

A step-down converter is presented. The step down converter includes a power stage having at least one phase, each phase comprising an inductor, a driver, and a clock source. The driver drives the power stage in a synchronous mode or in an asynchronous mode of operation with a minimum off time. When the output voltage approaches the input voltage of the converter, a duty cycle of the converter increases up to a value limited by the minimum off time. The clock source generates a first clock signal having a predefined pulse width. The driver generates a first stretchable clock signal having an adjustable pulse width and an adjustable period. Upon transition from the synchronous mode to the asynchronous mode the driver is configured to increase the adjustable pulse width and the period of the first stretchable clock signal.

First claim

The invention claimed is:

1 . A step-down converter configured to receive an input voltage and provide an output voltage, the step-down converter comprising:
a power stage having at least one phase, each phase comprising an inductor; a driver configured to drive the power stage in a synchronous mode or in an asynchronous mode of operation with a minimum off-time; wherein when the output voltage approaches the input voltage, a duty cycle of the converter increases up to a value limited by the minimum off-time; and a clock source configured to generate a first clock signal having a predefined pulse width; wherein the driver is configured to generate a first stretchable clock signal having an adjustable pulse width and an adjustable period; and wherein upon transition from the synchronous mode to the asynchronous mode the driver is configured to increase the adjustable pulse width and the period of the first stretchable clock signal.

2 . The step-down converter as claimed in claim 1 , wherein the driver comprises a first state machine configured to generate the first stretchable clock signal and adjust the pulse width and period of the first stretchable clock signal.

3 . The step-down converter as claimed in claim 2 , comprising:
a first ramp generator configured to generate a first ramp signal responsive to the first clock signal; and an error comparator configured to generate an error signal by comparing the output voltage with a reference voltage, wherein the pulse width of the stretchable clock signal increases as the error signal increases up to a limit value.

4 . The step-down converter as claimed in claim 3 , comprising a first comparator configured to compare the first ramp signal with the error signal, and wherein when the first ramp signal increases to become equal to the error signal the comparator trips and its output goes high.

5 . The step-down converter as claimed in claim 4 , wherein if the first clock signal occurs before the comparator trip event, then the converter transits to the asynchronous mode, otherwise the converter remains in the synchronous mode.

6 . The step-down converter as claimed in claim 2 , wherein the first state machine is configured to generate a first ramp reset signal to reset a first ramp signal; a first asynchronous mode signal indicating that the converter has transitioned into asynchronous mode; a first minimum off-time trigger signal configured to trigger a start of a timer; and a first magnetization request signal configured to start inductor magnetization after completion of the timer.

7 . The step-down converter as claimed in claim 2 , comprising a first logic circuit coupled to the first state machine.

8 . The step-down converter as claimed in claim 7 , wherein the first logic circuit comprises a plurality of persistence latches.

9 . The step-down converter as claimed in claim 7 , comprising a second state machine coupled to a second logic circuit; the second state machine being configured to generate a second stretchable clock signal having an adjustable pulse width and an adjustable period.

10 . The step-down converter as claimed in claim 9 , wherein the first logic circuit and the second logic circuit are configured to receive a logic signal for setting the state machine as a master or as a slave, such that when the first state machine is a master, the second state machine is a slave, and conversely when the first state machine is a slave, the second state machine is a master.

11 . The step-down converter as claimed in claim 9 , comprising a second ramp generator; wherein the second state machine is configured to generate a second ramp reset signal to reset the second ramp signal.

12 . The step-down converter as claimed in claim 9 , wherein the second state machine is configured to generate a second asynchronous mode signal indicating that the converter has transitioned into asynchronous mode; a second minimum off-time trigger signal configured to trigger a start of a timer; and a second magnetization request signal configured to start inductor magnetization after completion of the timer.

13 . The step-down converter as claimed in claim 1 , wherein the first clock signal and the first stretchable clock signal are in phase.

14 . The step-down converter as claimed in claim 1 , comprising a minimum off-time timer configured to start upon receipt of a trigger signal.

15 . A method of controlling a step-down converter configured to receive an input voltage and provide an output voltage, the method comprising
providing a driver configured to drive a power stage of the converter in a synchronous mode or in an asynchronous mode of operation with a minimum off-time; wherein when the output voltage approaches the input voltage, a duty cycle of the converter increases up to a value limited by the minimum off-time; generating a first clock signal having a predefined pulse width; generating a first stretchable clock signal having an adjustable pulse width and an adjustable period; and upon transition from the synchronous mode to the asynchronous mode, increasing the adjustable pulse width and the adjustable period of the stretchable clock signal.

16 . The method as claimed in claim 15 , comprising:
generating a first ramp signal responsive to the first clock signal; and generating an error signal by comparing the output voltage with a reference voltage; wherein the pulse width of the stretchable clock signal increases as the error signal increases up to a limit value.

17 . The method as claimed in claim 15 , comprising generating an enabling signal to enable a transition between the synchronous mode of operation to the asynchronous mode of operation.

18 . The method as claimed in claim 15 , comprising generating a magnetization request signal to magnetize the inductor.

19 . The method as claimed in claim 15 , wherein a magnetization of the inductor is caused by expiry of a minimum off-time timer.

20 . A controller for use with a step-down converter, the controller comprising:
a driver configured to drive a power stage of the converter in a synchronous mode or in an asynchronous mode of operation with a minimum off-time; wherein when the output voltage approaches the input voltage, a duty cycle of the converter increases up to a value limited by the minimum off-time; and a clock source configured to generate a first clock signal having a predefined pulse width; wherein the driver is configured to generate a first stretchable clock signal having an adjustable pulse width and an adjustable period; and wherein upon transition from the synchronous mode to the asynchronous mode the driver is configured to increase the adjustable pulse width and the period of the first stretchable clock signal.

Assignees

• Renesas Design Uk Ltd

Inventors

• Mercer Mark
• Kesterson John

Classifications

• H02M3/157 Primary

  with digital control · CPC title

• H02M3/158 Primary

  including plural semiconductor devices as final control devices for a single load · CPC title

• H02M3/075

  including a plurality of stages and two sets of clock signals, one set for the odd and one set for the even numbered stages · CPC title

• H02M3/072 Primary

  adapted to generate an output voltage whose value is lower than the input voltage · CPC title