Asynchronous dropout transition for multi-level and single-level buck converters

Patent metadata

Field	Value
Publication number	US-10998818-B2
Application number	US-201916533691-A
Country	US
Kind code	B2
Filing date	Aug 6, 2019
Priority date	Aug 6, 2019
Publication date	May 4, 2021
Grant date	May 4, 2021

Abstract

A multi-level buck converter is provided with seamless transitions back and forth from synchronous to asynchronous low dropout modes of operation.

First claim

What is claimed is:

1. A buck converter, comprising:
a first ramp signal generator configured to generate a first ramp signal responsive to a clock signal during a synchronous mode of operation and responsive to an asynchronous triggering signal during an asynchronous mode of operation;
a cycle timer configured to time a cycle timer period responsive to the asynchronous triggering signal, wherein the cycle timer period is less than or greater than a clock signal period for the clock signal;
a first comparator configured to compare the first ramp signal to an error signal to assert a first control signal responsive to the first ramp signal rising to equal to the error signal; and
a switch controller configured to determine if the first control signal is asserted prior to an expiration of the cycle timer period plus a minimum off-time period during the asynchronous mode of operation, and wherein the switch controller is further configured to transition to the synchronous mode of operation responsive to the expiration of the cycle timer period being sufficiently synchronous with the clock signal following a determination that the first control signal was asserted prior to an expiration of the cycle timer period plus a minimum off-time period.

2. The buck converter of claim 1 , wherein the switch controller is further configured to determine if the expiration of the cycle timer period was sufficiently synchronous with the clock signal by a determination of whether the expiration of the cycle timer period occurred during an on-time for the clock signal.

3. The buck converter of claim 2 , wherein a duty cycle for the clock signal is less than 50%.

4. The buck converter of claim 3 , wherein the duty cycle for the clock signal is approximately 20%.

5. The buck converter of claim 1 , wherein the buck converter comprises a single-level buck converter.

6. The buck converter of claim 1 , wherein the buck converter comprises a multi-level buck converter.

7. The multi-level buck converter of claim 6 , wherein the switch controller is further configured to control a transition from the synchronous mode of operation to the asynchronous mode of operation responsive to a count of synchronous cycles that are terminated responsive to the minimum-off-time period.

8. The multi-level buck converter of claim 7 , wherein the switch controller is further configured to control the transition from the synchronous mode of operation to the asynchronous mode of operation responsive to the count exceeding a threshold count.

9. The multi-level buck converter of claim 8 , wherein the switch controller is further configured to reset the count responsive to a synchronous switching cycle not being terminated responsive to the minimum off-time period.

10. The multi-level buck converter of claim 8 , wherein the threshold count is four.

11. The multi-level buck converter of claim 8 , wherein the switch controller is further configured to decrement the count responsive to a synchronous switching cycle not being terminated responsive to the minimum off-time period.

12. A method of controlling a buck converter, comprising:
during a synchronous mode of operation, generating a first ramp signal responsive to a clock signal;
during an asynchronous mode of operation, generating the first ramp signal responsive to an asynchronous triggering signal;
asserting a first control signal responsive to the first ramp signal rising to equal an error signal;
timing a cycle timer period responsive to the asynchronous triggering signal, wherein the cycle timer period is shorter than or greater than a clock signal period for the clock signal;
during the asynchronous mode of operation, determining if the first control signal was asserted prior to an expiration of the cycle timer period and an expiration of a minimum off-time period;
if the first control signal was asserted prior to the expiration of the cycle timer period and the expiration of the minimum off-time period, determining if a subsequent expiration of the cycle timer period is sufficiently synchronous with the clock signal; and
transitioning from the asynchronous mode of operation to the synchronous mode of operation responsive to a determination that the subsequent expiration of the cycle timer period is sufficiently synchronous with the clock signal.

13. The method of claim 12 , further comprising determining that the subsequent expiration of the cycle timer period is sufficiently synchronous with the clock signal by determining whether the subsequent expiration of the cycle timer period occurs during an on-time for the clock signal.

14. The method of claim 13 , wherein a duty cycle of the clock signal is less than 50%.

15. The method of claim 14 , wherein the duty cycle of the clock signal is approximately 20%.

16. The method of claim 12 , further comprising:
asserting a first magnetization signal responsive to the first ramp signal beginning a ramp signal period; and
de-asserting the first magnetization signal responsive to the assertion of the first control signal.

17. The method of claim 16 , wherein the buck converter is a multi-level buck converter, the method further comprising:
during the asynchronous mode of operation, asserting a third ramp signal having a slope that is twice that of the first ramp signal, wherein the assertion of the third ramp signal is synchronous with the first ramp signal beginning the ramp signal period;
determining whether the third ramp signal has risen to equal the error signal; and
asserting a second ramp signal responsive to the expiration of the minimum off-time period following a determination that the third ramp signal has risen to equal the error signal.

18. The method of claim 17 , further comprising:
generating a second magnetization signal responsive to a comparison of the second ramp signal to the error signal; and
controlling a plurality of four power switches responsive to the first magnetization signal and the second magnetization signal.

19. The method of claim 17 , further comprising:
comparing an output voltage for the multi-level buck converter to a reference voltage to generate the error signal.

20. The method of claim 16 , wherein asserting the first magnetizing signal comprises setting a first reset-set latch.

Assignees

• Dialog Semiconductor Uk Ltd

Inventors

• Kesterson John
• Mangudi Aravind
• Steele James
• Mercer Mark

Classifications

• H02M1/0095

  Hybrid converter topologies, e.g. NPC mixed with flying capacitor, thyristor converter mixed with MMC or charge pump mixed with buck · CPC title

• H02M3/07

  using capacitors charged and discharged alternately by semiconductor devices with control electrode {, e.g. charge pumps} · CPC title

• H02M1/0041

  Control circuits in which a clock signal is selectively enabled or disabled · CPC title

• H02M3/158 Primary

  including plural semiconductor devices as final control devices for a single load · CPC title

• H02M1/00

  Details of apparatus for conversion · CPC title