Redundant network system

US12506243B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12506243-B2
Application numberUS-202418744782-A
CountryUS
Kind codeB2
Filing dateJun 17, 2024
Priority dateMay 4, 2021
Publication dateDec 23, 2025
Grant dateDec 23, 2025

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A redundant network system includes a compute node having a network interface card includes a node port. The redundant network system includes a primary switch having a primary switch component and a primary switch port coupled to the primary switch component. The redundant network system includes a secondary switch having a secondary switch component and a secondary switch port coupled to the secondary switch component. The redundant network system includes a cable assembly having a node connector coupled to the node port, a primary connector coupled to the primary switch port, and a secondary connector coupled to the secondary switch port. The cable assembly includes a signal splitting circuit between the node connector and the primary and secondary connectors. The cable assembly includes a first cable between the signal splitting circuit and the primary connector and a second cable between the signal splitting circuit and the secondary connector.

First claim

Opening claim text (preview).

What is claimed is: 1 . A cable assembly for a redundant network system having a compute node having a node port, a primary switch having a primary switch port, and a secondary switch having a secondary switch port, the cable assembly comprising: a node connector configured to be coupled to the node port; a primary connector configured to be coupled to the primary switch port; a secondary connector configured to be coupled to the secondary switch port; a signal splitting circuit between the node connector and the primary and secondary connectors; a first cable coupled between the signal splitting circuit and the primary connector; and a second cable coupled between the signal splitting circuit and the secondary connector; wherein the first and second cables form redundant signal paths between the single node port of the compute node and the primary and secondary switch ports of the primary and secondary switches; wherein the redundant signal paths are operated on a serial communication protocol to control signaling along the first and second cables; and wherein the compute node forms a master device and the primary and secondary connectors form slave devices, wherein the first and second cables form redundant signal paths between the master device and the slave devices operated on an I2C protocol to control signaling along the first and second cables. 2 . The cable assembly of claim 1 , wherein the serial communication protocol for the redundant signal paths are operated on the I2C protocol. 3 . The cable assembly of claim 1 , wherein the cable assembly includes a first serial communication bus associated with the first cable extending between the signal splitting circuit and the primary connector, and wherein the cable assembly includes a second serial communication bus associated with the second cable extending between the signal splitting circuit and the secondary connector. 4 . The cable assembly of claim 3 , wherein the first and second serial communication buses are operated on the I2C protocol to control signaling along the first and second cables. 5 . The cable assembly of claim 3 , wherein the first and second serial communication buses are integrated into the first and second cables, respectively. 6 . The cable assembly of claim 3 , wherein the first serial communication bus enables and disables data communication along the first cable in accordance with the I2C protocol, and wherein the second serial communication bus enables and disables data communication along the second cable in accordance with the I2C protocol. 7 . The cable assembly of claim 6 , wherein the first serial communication bus is configured to operate in a primary mode of operation to enable data communication along the first cable and is configured to operate in a secondary mode of operation to disable data communication along the first cable, and wherein the second serial communication bus is configured to operate in a primary mode of operation to enable data communication along the second cable and is configured to operate in a secondary mode of operation to disable data communication along the second cable. 8 . The cable assembly of claim 3 , wherein the first serial communication bus includes a first serial data line to send and receive data between the signal splitting circuit and the primary connector and includes a first serial clock line that carries a clock signal between the signal splitting circuit and the primary connector, and wherein the second serial communication bus includes a second serial data line to send and receive data between the signal splitting circuit and the secondary connector and includes a second serial clock line that carries a clock signal between the signal splitting circuit and the secondary connector. 9 . The cable assembly of claim 1 , wherein the cable assembly splits the signals from the compute node to the primary and secondary switches without an electronic switching device. 10 . The cable assembly of claim 1 , wherein the signal splitting circuit includes a splitter having a single input, a first output, and a second output, the input being electrically coupled to the node connector, the first output being electrically coupled to the first cable, the second output being electrically coupled to the second cable. 11 . The cable assembly of claim 1 , wherein the signal splitting circuit includes a splitter having a single input, a first output, and a second output, the signal splitting circuit includes a first signal conditioner electrically coupled to the first output and a second signal conditioner electrically coupled to the second output. 12 . The cable assembly of claim 11 , wherein the input is electrically coupled to the node connector, the first cable being electrically coupled to the first signal conditioner, the second cable being electrically coupled to the second signal conditioner. 13 . The cable assembly of claim 11 , wherein the first signal conditioner includes a first retimer and the second signal conditioner includes a second retimer. 14 . A cable assembly for a redundant network system having a compute node having a node port, a primary switch having a primary switch port, and a secondary switch having a secondary switch port, the cable assembly comprising: a node connector configured to be coupled to the node port; a primary connector configured to be coupled to the primary switch port; a secondary connector configured to be coupled to the secondary switch port; a signal splitting circuit between the node connector and the primary and secondary connectors; a first cable coupled between the signal splitting circuit and the primary connector, the first cable including a first serial communication bus extending between the signal splitting circuit and the primary connector; and a second cable coupled between the signal splitting circuit and the secondary connector, the second cable including a second serial communication bus extending between the signal splitting circuit and the secondary connector; wherein the first and second cables form redundant signal paths between the single node port of the compute node and the primary and secondary switch ports of the primary and secondary switches; wherein the redundant signal paths are operated on a serial communication protocol to control signaling along the first and second serial communication busses of the first and second cables to control signaling along the first and second cables; and wherein the first and second serial communication buses are integrated into the first and second cables, respectively. 15 . The cable assembly of claim 14 , wherein the serial communication protocol for the redundant signal paths are an I2C protocol. 16 . The cable assembly of claim 14 , wherein the first serial communication bus enables and disables data communication along the first cable in accordance with the I2C protocol, and wherein the second serial communication bus enables and disables data communication along the second cable in accordance with the I2C protocol. 17 . The cable assembly of claim 16 , wherein the first serial communication bus is configured to operate in a primary mode of operation to enable data communication along the first cable and is configured to operate in a secondary mode of operation to disable data communication along the first cable, and wherein the second serial communication bus is configured to operate in a primary mode of operation to enable data communication along the second cable and is configured to operate in a secondary mode

Assignees

Inventors

Classifications

  • Pair constructions · CPC title

  • the coupling part being secured only to wires or cables · CPC title

  • H01P5/12Primary

    Coupling devices having more than two ports (H01P5/04 takes precedence) · CPC title

  • H01R31/02Primary

    Intermediate parts for distributing energy to two or more circuits in parallel, e.g. splitter (with a holder adapted for supporting apparatus to which its counterpart is attached H01R33/92) · CPC title

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What does patent US12506243B2 cover?
A redundant network system includes a compute node having a network interface card includes a node port. The redundant network system includes a primary switch having a primary switch component and a primary switch port coupled to the primary switch component. The redundant network system includes a secondary switch having a secondary switch component and a secondary switch port coupled to the …
Who is the assignee on this patent?
Te Connectivity Solutions Gmbh
What technology area does this patent fall under?
Primary CPC classification H01P5/12. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Dec 23 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).