On-package die-to-die (D2D) interconnect for memory using universal chiplet interconnect express (UCIe) PHY

Patent metadata

Field	Value
Publication number	US-12505065-B2
Application number	US-202318399463-A
Country	US
Kind code	B2
Filing date	Dec 28, 2023
Priority date	Mar 18, 2023
Publication date	Dec 23, 2025
Grant date	Dec 23, 2025

Abstract

Embodiments described herein may include apparatus, systems, techniques, or processes that are directed to on-package die-to-die (D2D) interconnects. Specifically, embodiments herein may relate to on-package D2D interconnects for memory that use or relate to the Universal Chiplet Interconnect Express (UCIe) adapter or physical layer (PHY). Other embodiments are described and claimed.

First claim

What is claimed is:

1 . An apparatus, comprising:
a system-on-a-chip (SoC) comprising an integrated circuit on a semiconductor die, the SoC comprising a memory controller and a universal chiplet interconnect express (UCIe) interface for a UCIe interconnect, the UCle interface comprising interface logic to manage transport of data over the UCIe interconnect in a transmit mode, the interface logic to: decode memory signals from the memory controller; map the memory signals to UCle signals; and encode the UCle signals for transmission over a transmit channel of the UCle interconnect.

2 . The apparatus of claim 1 , the interface logic to manage transport of data over the UCle interconnect in a receive mode, the interface logic to:
decode UCle signals from a receive channel of the UCIe interconnect; map the UCle signals to memory signals; and encode the memory signals for transmission to the memory controller.

3 . The apparatus of claim 1 , wherein the memory signals are double data rate (DDR) memory signals or high bandwidth memory (HBM) memory signals.

4 . The apparatus of claim 1 , wherein the memory signals comprise double data rate (DDR) physical layer (PHY) interface (DFI) signals, and the interface logic to:
map DFI command and data timing signals to UCle command and data timing signals for a UCle PHY interface; and map UCle command and data timing signals for the UCIe PHY interface to DFI command and data timing signals.

5 . The apparatus of claim 1 , the interface logic to:
encode the UCle signals for transmission over the transmit channel of the UCIe interconnect to a memory chip in a same package as the SoC; and decode the UCIe signals from the receive channel of the UCIe interconnect from the memory chip in the same package as the SoC.

6 . The apparatus of claim 1 , the interface logic to:
encode cyclic redundancy check (CRC) or error checking and correcting (ECC) signals for the UCle signals for transmission over a command channel of the UCIe interconnect; and decode the CRC signals or ECC signals for the UCle signals from the command channel of the UCIe interconnect.

7 . The apparatus of claim 1 , the interface logic to:
encode the UCle signals for transmission over multiple transmit channels of the UCIe interconnect; and decode the UCIe signals from multiple receive channels of the UCIe interconnect.

8 . The apparatus of claim 1 , comprising:
a second (SoC) comprising a memory controller and a second UCIe interconnect, the second UCIe interconnect comprising second interface logic to manage transport of data over the second UCIe interconnect in a transmit mode and a receive mode, the second interface logic to: encode UCIe signals for transmission over a transmit channel of the second UCIe interconnect to a second memory chip in a same package as the second SoC; and decode the UCIe signals from a receive channel of the second UCIe interconnect from the second memory chip in the same package as the second SoC.

9 . The apparatus of claim 1 , the interface logic to:
encode UCIe signals for transmission over the transmit channel of the UCIe interconnect through buffered logic of a first memory chip in a same package as the SoC for a second memory chip in the same package as the SoC and the first memory chip; and decode the UCle signals from a receive channel of the UCIe interconnect from the second memory chip through the buffered logic of the first memory chip.

10 . An apparatus, comprising:
a system-on-a-chip (SoC) fabric of a SoC comprising an integrated circuit on a semiconductor die, the SoC fabric comprising a universal chiplet interconnect express (UCIe) interface for a UCIe interconnect, the UCle interface comprising interface logic to manage transport of data over the UCle interconnect in a transmit mode, the interface logic to: decode memory signals from over the SoC fabric; map the memory signals to UCle signals; and encode the UCle signals for transmission over an asymmetric link of the UCle interconnect.

11 . The apparatus of claim 10 , the interface logic to manage transport of data over the UCle interconnect in a receive mode, the interface logic to:
decode UCIe signals from the asymmetric link of the UCIe interconnect; map the UCle signals to memory signals; and encode the memory signals for transmission over the SoC fabric.

12 . The apparatus of claim 10 , wherein the memory signals are compute express link (CXL) memory signals.

13 . The apparatus of claim 10 , wherein the memory signals compute express link (CXL) signals, and the interface logic to:
map CXL command and data timing signals for a CXL memory interface to UCle command and data timing signals for a UCle adapter and physical layer (PHY) interface; and map UCle command and data timing signals for the UCle adapter and PHY interface to CXL command and data timing signals for the CXL memory interface.

14 . The apparatus of claim 10 , the interface logic to:
encode the UCle signals for transmission over the asymmetric link of the UCle interconnect to a memory chip in a same package as the SoC fabric; and decode the UCle signals from the asymmetric link of the UCIe interconnect from the memory chip in the same package as the SoC fabric.

15 . The apparatus of claim 10 , the interface logic to:
encode cyclic redundancy check (CRC) or error checking and correcting (ECC) signals for the UCle signals for transmission over the asymmetric link of the UCle interconnect; and decode the CRC signals or ECC signals for the UCle signals from the asymmetric link of the UCIe interconnect.

16 . A method, comprising:
decoding memory signals from a memory controller of a system-on-a-chip (SoC) comprising an integrated circuit on a semiconductor die, the SoC comprising the memory controller and a universal chiplet interconnect express (UCle) interface for a UCIe interconnect, the UCle interface comprising interface logic to manage transport of data over the UCIe interconnect in a transmit mode; mapping the memory signals to UCle signals; and encoding the UCle signals for transmission over a transmit channel of the UCle interconnect.

17 . The method of claim 16 , comprising:
decoding UCIe signals from a receive channel of the UCle interconnect by the interface logic in a receive mode; mapping the UCle signals to memory signals; and encoding the memory signals for transmission to the memory controller.

18 . The method of claim 16 , wherein the memory signals are double data rate (DDR) memory signals or high bandwidth memory (HBM) memory signals.

19 . The method of claim 16 , wherein the memory signals comprise double data rate (DDR) physical layer (PHY) interface (DFI) signals, and the interface logic to:
mapping DFI command and data timing signals to UCle command and data timing signals for a UCle PHY interface; and mapping UCle command and data timing signals for the UCle PHY interface to DFI command and data timing signals.

20 . The method of claim 16 , comprising:
encoding the UCle signals for transmission over the transmit channel of the UCIe interconnect to a memory chip in a same package as the SoC; and decoding the UCle signals from the receive channel of the UCle interconnect from the memory chip in the same package as the SoC.

Assignees

• Intel Corp

Inventors

• Das Sharma Debendra
• Lanka Narasimha
• Onufryk Peter
• Choudhary Swadesh
• Pasdast Gerald
• Wu Zuoguo
• Ziakas Dimitrios
• Muthrasanallur Sridhar

Classifications

• H10W90/00

  Package configurations · CPC title

• G06F13/1689

  Synchronisation and timing concerns (synchronisation on a memory bus G06F13/4234) · CPC title

• G06F2213/0038

  System on Chip · CPC title

• G06F2213/0064

  Latency reduction in handling transfers · CPC title

• G06F13/1668

  Details of memory controller · CPC title