Dual magnetic tunnel junction devices for magnetic random access memory (MRAM)

Patent metadata

Field	Value
Publication number	US-12501836-B2
Application number	US-202217981734-A
Country	US
Kind code	B2
Filing date	Nov 7, 2022
Priority date	Aug 7, 2018
Publication date	Dec 16, 2025
Grant date	Dec 16, 2025

Abstract

A dual magnetic tunnel junction (DMTJ) is disclosed with a PL1/TB1/free layer/TB2/PL2 configuration wherein a first tunnel barrier (TB1) has a substantially lower resistance×area (RA 1 ) product than RA 2 for an overlying second tunnel barrier (TB2) to provide an acceptable magnetoresistive ratio (DRR). Moreover, first and second pinned layers, PL1 and PL2, respectively, have magnetizations that are aligned antiparallel to enable a lower critical switching current that when in a parallel alignment. The condition RA1<RA2 is achieved with one or more of a smaller thickness and a lower oxidation state for TB1 compared with TB2, with conductive (metal) pathways formed in a metal oxide or metal oxynitride matrix for TB1, or with a TB1 containing a dopant to create conducting states in the TB1 band gap. Alternatively, TB1 may be replaced with a metallic spacer to improve conductivity between PL1 and the FL.

First claim

What is claimed is:

1 . A device comprising:
a first pinned ferromagnetic layer on a substrate; a metallic spacer disposed on the first pinned ferromagnetic layer; a free layer that contacts a top surface of the metallic spacer and having a magnetization aligned orthogonal to the substrate; a tunnel barrier layer adjoining a top surface of the free layer; and a second pinned ferromagnetic layer disposed on the tunnel barrier layer, wherein the second pinned ferromagnetic layer has a magnetization aligned orthogonal to the substrate, and antiparallel to a magnetization of the first pinned ferromagnetic layer.

2 . The device of claim 1 , wherein the metallic spacer is formed of a material selected from the group consisting of Cu, Cr, Ag, Ge and alloys thereof.

3 . The device of claim 1 , wherein the tunnel barrier layer is formed of a metal oxide in which the metal is selected from one or more of Mg, Ti, Al, Zn, Zr, Hf, and Ta.

4 . The device of claim 1 , wherein the metallic spacer has a first resistance×area product, and
wherein the tunnel barrier layer has a second resistance×area product that is greater than the first resistance×area product.

5 . The device of claim 1 , further comprising:
a seed layer disposed on the substrate and interfacing with the first pinned ferromagnetic layer; and a hard mask layer disposed over and interfacing with the second pinned ferromagnetic layer.

6 . The device of claim 1 , wherein the tunnel barrier layer has a higher oxidation state than the metallic spacer layer.

7 . The device of claim 1 , wherein the device is a memory device selected from the group consisting of magnetic random access memory (MRAM) and a spin torque (STT)-MRAM.

8 . A device comprising:
a first pinned ferromagnetic layer disposed over a substrate; a metallic spacer disposed over the first pinned ferromagnetic layer, wherein the metallic spacer has a first resistance×area product; a free layer disposed over the metallic spacer; a tunnel barrier layer disposed over the free layer, wherein the tunnel barrier layer has a second resistance×area product that is greater than the first resistance×area product; and a second pinned ferromagnetic layer disposed over the tunnel barrier layer.

9 . The device of claim 8 , wherein the second pinned ferromagnetic layer has a magnetization aligned antiparallel to a magnetization of the first pinned ferromagnetic layer.

10 . The device of claim 9 , wherein the magnetization of the second pinned ferromagnetic layer is aligned orthogonal to the substrate.

11 . The device of claim 8 , wherein the metallic spacer includes a first metal and the tunnel barrier layer includes a second metal that is different than the first metal.

12 . The device of claim 8 , wherein the tunnel barrier layer includes a metal oxide material.

13 . The device of claim 8 , wherein the tunnel barrier layer includes a metal oxynitride material.

14 . The device of claim 8 , wherein the metallic spacer interfaces with the free layer and the free layer interfaces with the tunnel barrier layer.

15 . The device of claim 14 , wherein the metallic spacer interfaces with the first pinned ferromagnetic layer and the tunnel barrier layer interfaces with the second pinned ferromagnetic layer.

16 . A device comprising:
a first pinned layer disposed on a substrate; a metallic spacer disposed on the first pinned layer, wherein the metallic spacer has a first resistance×area product; a free layer disposed on and physically contacting the metallic spacer; a tunnel barrier layer disposed on and physically contacting the free layer, wherein the tunnel barrier layer has a second resistance×area product that is greater than the first resistance×area product; and a second pinned layer disposed on the tunnel barrier layer.

17 . The device of claim 16 , wherein the first pinned layer physically contacts the metallic spacer and the second pinned layer physically contacts the tunnel barrier layer.

18 . The device of claim 17 , further comprising a conductive material layer disposed on and physically contacting the second pinned layer.

19 . The device of claim 16 , wherein the metallic spacer includes a first material selected from the group consisting of Cu, Cr, Ag and Ge,
wherein the tunnel barrier layer includes a second material selected from the group consisting of Mg, Ti, Al, Zn, Zr, Hf, and Ta.

20 . The device of claim 16 , wherein the second pinned ferromagnetic layer has a magnetization aligned antiparallel to a magnetization of the first pinned ferromagnetic layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Sundar Vignesh
• Wang Yu-Jen
• Thomas Luc
• Jan Guenole

Classifications

• H10N50/85

  Materials of the active region · CPC title

• H10N50/80

  Constructional details · CPC title

• H10N50/01

  Manufacture or treatment · CPC title

• H10B61/00

  Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices · CPC title

• G11C11/161 Primary

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title