Semiconductor device for a low-loss antenna switch

Patent metadata

Field	Value
Publication number	US-12501692-B2
Application number	US-202418773203-A
Country	US
Kind code	B2
Filing date	Jul 15, 2024
Priority date	Jul 12, 2019
Publication date	Dec 16, 2025
Grant date	Dec 16, 2025

Abstract

A semiconductor device includes a substrate, a first metal-oxide-semiconductor device and a at least one first resistor. The substrate includes a non-doped region. The first metal-oxide-semiconductor device extends into the substrate. The first metal-oxide-semiconductor device is adjacent to the non-doped region. The at least one first resistor is disposed right above the non-doped region and arranged in a first row aligned with the first metal-oxide-semiconductor device in a first direction.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a substrate comprising a non-doped region; a first transistor adjacent to the non-doped region in a first direction; a first resistor coupled to the first transistor and disposed right above the non-doped region; a second transistor adjacent to the non-doped region in the first direction and aligned with the first transistor along a second direction perpendicular to the first direction in a top view; and a second resistor coupled to the second transistor and disposed right above the non-doped region, wherein the second resistor is separated from the first resistor along the second direction in the top view, wherein the first resistor is one of a plurality of first resistors separated from each other by a distance ranging from about 0.001 to about 10 micrometers along the first direction.

2 . The semiconductor device of claim 1 , wherein each of the plurality of first resistors has a width ranging from about 0.001 to about 10 micrometers and a minimum resistance of about 500 ohms.

3 . The semiconductor device of claim 1 , wherein the second transistor is separated from the first transistor by a distance ranging from about 0.001 to about 5 micrometers along the second direction.

4 . The semiconductor device of claim 1 , further comprising:
a third resistor, wherein the first resistor is arranged at a first side of the first transistor and the third resistor is arranged at a second side, of the first transistor, opposite to the first side.

5 . The semiconductor device of claim 1 , further comprising:
a plurality of transistors, wherein the first transistor and the second transistor are part of the plurality of transistors, wherein each of the plurality of transistors is separated from an adjacent transistor by a predetermined spacing.

6 . The semiconductor device of claim 1 , further comprising:
an isolation extending into the substrate, wherein the substrate further comprises a lower portion, and the non-doped region is interposed between the isolation and the lower portion.

7 . The semiconductor device of claim 1 , further comprising:
a metal layer disposed above the first transistor and the second transistor.

8 . A semiconductor device, comprising:
a substrate comprising a non-doped region; a first transistor adjacent to the non-doped region in a first direction in a top view; a first resistor coupled to the first transistor and disposed above the non-doped region; and a second resistor coupled to the first transistor and disposed above the non-doped region, wherein the first transistor, the first resistor and the second resistor are aligned with each other along the first direction in the top view, wherein each of the first and second resistors has a width ranging from about 0.001 to about 10 micrometers and has a minimum resistance of about 500 ohms.

9 . The semiconductor device of claim 8 , further comprising:
a second transistor separated from the first transistor along a second direction that is perpendicular to the first direction.

10 . The semiconductor device of claim 9 , further comprising:
a plurality of third resistors disposed right above the non-doped region and arranged in a row aligned with the second transistor in the first direction.

11 . The semiconductor device of claim 8 , further comprising:
an isolation extending into the substrate, wherein the substrate further comprises a lower portion, and the non-doped region is interposed between the isolation and the lower portion.

12 . The semiconductor device of claim 8 , further comprising:
a plurality of resistors, wherein the first and second resistors are part of the plurality of resistors, wherein each of the plurality of resistors is separated from an adjacent resistor by a predetermined spacing.

13 . The semiconductor device of claim 8 , further comprising:
a metal layer disposed above the first transistor.

14 . A semiconductor device, comprising:
a substrate comprising a non-doped region; a first transistor adjacent to the non-doped region in a first direction; a first resistor coupled to the first transistor and disposed above the non-doped region; a second resistor coupled to the first transistor and disposed above the non-doped region, wherein the first transistor, the first resistor and the second resistor are aligned with each other along the first direction in a top view; a second transistor adjacent to the non-doped region in the first direction and aligned with the first transistor along a second direction perpendicular to the first direction in the top view; and a third resistor, wherein the first resistor is arranged at a first side of the first transistor and the third resistor is arranged at a second side, of the first transistor, opposite to the first side.

15 . The semiconductor device of claim 14 , wherein the first resistor is one of a plurality of first resistors, wherein each of the plurality of first resistors has a width ranging from about 0.001 to about 10 micrometers and a minimum resistance of about 500 ohms.

16 . The semiconductor device of claim 14 , wherein the second transistor is separated from the first transistor by a distance ranging from about 0.001 to about 5 micrometers along the second direction.

17 . The semiconductor device of claim 14 , wherein the first resistor is one of a plurality of first resistors separated from each other by a distance ranging from about 0.001 to about 10 micrometers along the first direction.

18 . The semiconductor device of claim 14 , further comprising:
a plurality of transistors, wherein the first transistor and the second transistor are part of the plurality of transistors, wherein each of the plurality of transistors is separated from an adjacent transistor by a predetermined spacing.

19 . The semiconductor device of claim 14 , further comprising:
an isolation extending into the substrate, wherein the substrate further comprises a lower portion, and the non-doped region is interposed between the isolation and the lower portion.

20 . The semiconductor device of claim 14 , further comprising:
a metal layer disposed above the first transistor and the second transistor.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Jin Jun-De
• Yeh Tzu-Jin

Classifications

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W44/248

  for antennas · CPC title

• H10W74/137

  the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence) · CPC title

• H10D64/519

  characterised by their top-view geometrical layouts · CPC title