High speed interface protection apparatus

Patent metadata

Field	Value
Publication number	US-9673187-B2
Application number	US-201514796731-A
Country	US
Kind code	B2
Filing date	Jul 10, 2015
Priority date	Apr 7, 2015
Publication date	Jun 6, 2017
Grant date	Jun 6, 2017

Abstract

The disclosed technology relates to electronics, and more particularly, to protection devices that protect circuits from transient electrical events such as electrical overstress/electrostatic discharge. A protection device includes a semiconductor substrate having formed therein at least two wells and a deep well underlying and contacting the at least two wells. The device additionally includes a first PN diode formed in one of the at least two wells and having a first heavily doped region of a first conductivity type and a first heavily doped region of a second conductivity type, and includes a second PN diode formed in one of the at least two wells and having a second heavily doped region of the first conductivity type and a second heavily doped region of the second conductivity type. The device additionally includes a first PN diode and the second PN diode are electrically shorted by an electrical shorting structure to form a first plurality of serially connected diodes having a threshold voltage. The device further includes a PNPN silicon-controlled rectifier (SCR) having a trigger voltage and comprising the first heavily doped region of the first conductivity type, the at least two wells, the deep well, and the second heavily doped region of the second conductivity type.

First claim

What is claimed is:

1. An integrated circuit device, comprising:
a semiconductor substrate having formed therein at least two wells and a deep well underlying and contacting the at least two wells;
a first PN diode formed in one of the at least two wells and comprising a first heavily doped region of a first conductivity type and a first heavily doped region of a second conductivity type;
a second PN diode formed in another one of the at least two wells and comprising a second heavily doped region of the first conductivity type and a second heavily doped region of the second conductivity type,
wherein the first PN diode and the second PN diode are electrically shorted by an electrical shorting structure to form a first plurality of serially connected diodes having a threshold voltage; and
a PNPN silicon-controlled rectifier (SCR) having a trigger voltage and comprising the first heavily doped region of the first conductivity type, the at least two wells, the deep well, and the second heavily doped region of the second conductivity type.

2. The integrated circuit device of claim 1 wherein doping concentrations of the wells, distances between adjacent ones of the heavily doped regions, and an electrical resistance of the electrical shorting structures are such that the threshold voltage is lower than the trigger voltage.

3. The integrated circuit device of claim 1 , wherein:
the semiconductor substrate is a p-type semiconductor substrate, and wherein the at least two wells include an N well and a P well laterally adjacent to the N well, and the deep well is a deep N well,
the first heavily doped region of the first conductivity type is a first p + region and the first heavily doped region of the second conductivity type is a first n + region, the first p + region and the first n + region each formed in the N well,
the second heavily doped region of the first conductivity type is a second p + region and the second heavily doped region of the second conductivity type is a second n + region, the second p + region and the second n + region each formed in the P well, and
wherein the electrical shorted structure comprises a metallization structure contacting the first + region and the second p + region.

4. The integrated circuit device of claim 3 , further comprising:
a second N well formed laterally adjacent the P well such that the P well is interposed between the N well and the second N well, the deep N well laterally extending further to contact the second N well;
a third PN diode comprising a third p + region and the second n + region each formed in the P well;
a fourth PN diode comprising a fourth p + region and a third n + region each formed in the second N well;
a second metallization structure contacting the third n + region and the third p + region to form an electrical short therebetween such that the third PN diode and the fourth PN diode form a second plurality of serially connected diodes having a second threshold voltage; and
a second PNPN silicon-controlled rectifier (SCR) having a second trigger voltage comprising the fourth p+ region, the second N well, the deep N well, the P well and the second n + region,
wherein the doping concentrations of the wells, distances between adjacent ones of the heavily doped regions and the metallization structures are such that the second threshold voltage is lower than the second trigger voltage.

5. The integrated circuit device of claim 4 , wherein the first n + region, the second p + region, the N well and the P well have doping concentrations such when the first n + region is at a higher voltage than the second p + region, an electrical path from the first n + region to the second p + region through the N well region and the P well region has a substantially higher electrical resistance than the electrical resistance of the metallization structure shorting the first n+ region and the second p + region.

6. The integrated circuit device of claim 5 , wherein the first to third n + regions and the first to fourth p + regions are each doped to have active dopant concentrations between about 1×10 20 cm −3 and about 8×10 20 cm −3 , and wherein the N well, the P well, the second N well and the deep N well are each doped to have active dopant concentrations between about 1.5×10 16 cm −3 and about 7.5×10 16 cm −3 , and wherein a total resistance of each of the metallization structure is between about 100 Ohms and about 1000 Ohms.

7. The integrated circuit device of claim 4 , wherein each of the first p + region and the fourth p + region is connected to a first terminal serving as a common anode and the second n + region is connected to a second terminal serving as a common cathode, the common anode and the common cathode being common for the first and second serially connected diodes and the first and second PNPN SCRs.

8. The integrated circuit device of claim 7 , wherein:
the first PN diode further comprises a first electrically floating metal layer formed over a surface of the N well between the first p + region and the first n + region;
the second PN diode further comprises a second electrically floating metal layer formed over a surface of the P well between the second p+ region and the second n + region;
the third PN diode further comprises a third electrically floating metal layer formed over the surface of the P well between the third p + region and the second n + region; and
the fourth PN diode further comprises a fourth electrically floating metal layer formed over a surface of the second N well between the fourth p+ region and the third n + region.

9. The integrated circuit device of claim 8 , wherein each of the first through fourth electrically floating metal layers are separated from the underlying surface of the respective well by an intervening insulating oxide.

10. The integrated circuit device of claim 8 , further comprising a fifth electrically floating metal layer formed between the first n+ region and the second p + region and crossing a junction formed between the N well and the P well, and a sixth electrically floating metal layer formed between the third p + region and the third n+ region and crossing a junction formed between the P well and the second N well.

11. The integrated circuit device of claim 7 , wherein:
the first PN diode further comprises a first dielectric isolation formed in the NW between the first p+ region and the first n + region;
the second PN diode further comprises a second dielectric isolation formed in the PW between the second p + region and the second n + region;
the third PN diode further comprises a third dielectric isolation formed in the PW between the third p + region and the second n + region; and
the fourth PN diode further comprises a fourth dielectric isolation formed in the second NW between the fourth p + region and the third n + region.

12. The integrated circuit device of claim 4 , further comprising:
a second P well at an outer side of the N well opposite a side facing the P well;
a third N well at an outer side of the second P well opposite a side facing the P well;
a third P well at an outer side of the second N well opposite a side facing the P well; and
a fourth N well at an outer side of the third P well opposite a side facing the P well,
wherein each of the second P well, the third N well, the third P well and the fourth N well has formed therein an additional diode comprising a p + region, an n + region, and an electrically floating metal layer formed over a surface of the respective well between the p + region and the n + region,
wherein the first plurality of serially connected diodes i

Assignees

• Analog Devices Inc

Inventors

• Salcedo Javier Alejandro
• Pfeifer Jonathan

Classifications

• H01L27/0259 Primary

  Electricity · mapped topic

• H01L27/0207

  Electricity · mapped topic

• H01L27/0262

  Electricity · mapped topic

• H10D89/713

  including a PNP transistor and a NPN transistor, wherein each of said transistors has its base region coupled to the collector region of the other transistor, e.g. silicon controlled rectifier [SCR] devices · CPC title

• H10D89/10

  Integrated device layouts · CPC title