Silicon carbide power semiconductor device having reduced specific on-resistance

Patent metadata

Field	Value
Publication number	US-12501674-B2
Application number	US-202217931034-A
Country	US
Kind code	B2
Filing date	Sep 9, 2022
Priority date	Oct 14, 2021
Publication date	Dec 16, 2025
Grant date	Dec 16, 2025

Abstract

A silicon carbide power semiconductor device is provided, including a substrate, a drift region, a body region, a source region, a base region, a shielding region, a JFET region, a gate structure, an insulating layer, and a source metal layer. The source contacting window has first edges within second edges of the body region corresponding to the first edges, and the source metal layer abuts only a part of the source region. The area of the silicon carbide power semiconductor device of the present disclosure is thus reduced. Therefore, the ratio of the channel length to the area of the silicon carbide power semiconductor device and the ratio of the area of the JFET region to the area of the silicon carbide power semiconductor device are increased, whereby the specific on-resistance of the silicon carbide power semiconductor device is reduced.

First claim

What is claimed is:

1 . A silicon carbide power semiconductor device, comprising:
a substrate, which is of a first dopant type; a drift region disposed on the substrate, wherein the drift region is of the first dopant type; a body region disposed in the drift region, which is of a second dopant type; a source region surrounding the body region, wherein the source region is of the first dopant type; a base region surrounding the source region, wherein the base region is of the second dopant type; a shielding region surrounding the body region and disposed under the source region and the base region, wherein the shielding region is of the second dopant type; a junction field effect transistor (JFET) region surrounding the base region and the shielding region; a gate structure formed above the JFET region, the base region and a part of the source region; an insulating layer, formed above the JFET region, the base region, and a part of the source region; a source contacting window, which penetrates the insulating layer, and has at least one first edge closer to a center of the body region than at least one second edge of the body region that is parallel to the first edge; and a source metal layer, filled in the source contacting window.

2 . The silicon carbide power semiconductor device according to claim 1 , wherein the source contacting window has two first edges closer to the center of the body region than two second edges of the body region corresponding to the first edges, and the source contacting window is symmetrical with respect to an axis of the body region.

3 . The silicon carbide power semiconductor device according to claim 1 , wherein the source contacting window has three first edges closer to the center of the body region than three second edges of the body region corresponding to the first edges.

4 . The silicon carbide power semiconductor device according to claim 1 , wherein a distance between an edge of the body region and an inner edge of the gate structure ranges from 0.5 μm to 0.6 μm.

5 . The silicon carbide power semiconductor device according to claim 1 , wherein a distance between an edge of the body region and an outer edge of the source region ranges from 1.0 μm to 1.1 μm.

6 . The silicon carbide power semiconductor device according to claim 1 , wherein a distance between an edge of the source contacting window and an inner edge of the gate structure ranges from 0.8 μm to 0.9 μm.

7 . The silicon carbide power semiconductor device according to claim 1 , wherein a distance between the body region and an edge of the source contacting window outside the body region ranges from 1.0 μm to 1.1 μm.

8 . The silicon carbide power semiconductor device according to claim 1 , wherein a distance between an inner edge of the gate structure and an outer edge of the base region ranges from 1.0 μm to 1.1 μm.

9 . The silicon carbide power semiconductor device according to claim 1 , wherein a distance between an outer edge of the source region and an outer edge of the base region ranges from 0.5 μm to 0.6 μm.

10 . The silicon carbide power semiconductor device according to claim 1 , wherein a distance between an outer edge of the base region and an outer edge of the JFET region ranges from 0.5 μm to 0.6 μm.

11 . The silicon carbide power semiconductor device according to claim 1 , wherein the body region has a width ranging from 1.8 μm to 2.0 μm.

12 . The silicon carbide power semiconductor device according to claim 1 , wherein the body region has a doping concentration greater than that of the shielding region, and the shielding region has a doping concentration greater than that of the base region.

13 . The silicon carbide power semiconductor device according to claim 1 , wherein the JFET region has a doping concentration greater than that of the drift region.

14 . The silicon carbide power semiconductor device according to claim 1 , wherein the silicon carbide power semiconductor device has a channel density greater than or equal to 0.48 μm −1 , and a JFET density greater than or equal to 0.29, wherein the JFET region has a specific on-resistance smaller than or equal to 3.6 mΩ·cm 2 .

Assignees

• Silicon Magic Semiconductor Tech Hangzhou Co Ltd
• Hangzhou Silicon Magic Semiconductor Tech Co Ltd

Inventors

• Yang Xiao
• Chen Hui

Classifications

• H10D64/258

  characterised by the relative positions of the source or drain electrodes with respect to the gate electrode · CPC title

• H10D64/252

  for vertical or pseudo-vertical devices · CPC title

• H10D62/8325 Primary

  Silicon carbide · CPC title

• H10D62/154

  Dispositions · CPC title

• H10D30/66 Primary

  Vertical DMOS [VDMOS] FETs · CPC title