Integrated circuit structures having differentiated channel sizing

Patent metadata

Field	Value
Publication number	US-12501661-B2
Application number	US-202217700002-A
Country	US
Kind code	B2
Filing date	Mar 21, 2022
Priority date	Mar 21, 2022
Publication date	Dec 16, 2025
Grant date	Dec 16, 2025

Abstract

Embodiments of the present disclosure include integrated circuit structures having differentiated channel sizing, and methods of fabricating integrated circuit structures having differentiated channel sizing. In an example, a structure includes a memory region having a first vertical stack of horizontal nanowires having a first number of nanowires. The integrated circuit structure also includes a logic region having a second vertical stack of horizontal nanowires spaced apart from the first vertical stack of horizontal nanowires. The second vertical stack of horizontal nanowires has a second number of nanowires less than the first number of nanowires.

First claim

What is claimed is:

1 . An integrated circuit structure, comprising:
a memory region having a first vertical stack of horizontal nanowires having a first number of nanowires; and a logic region having a second vertical stack of horizontal nanowires spaced apart from the first vertical stack of horizontal nanowires, the second vertical stack of horizontal nanowires having a second number of nanowires less than the first number of nanowires, wherein a top nanowire of the second vertical stack of horizontal nanowires is at same level as a top nanowire of the first vertical stack of horizontal nanowires.

2 . The integrated circuit structure of claim 1 , wherein the first number of nanowires is four, and the second number of nanowires is three.

3 . The integrated circuit structure of claim 1 , further comprising a first gate structure portion over the first vertical stack of horizontal nanowires, a second gate structure portion over the second vertical stack of horizontal nanowires, and a gate cut between the first gate structure portion and the second gate structure portion.

4 . The integrated circuit structure of claim 3 , further comprising a dielectric gate plug in the gate cut.

5 . The integrated circuit structure of claim 1 , wherein the memory region further comprises a third vertical stack of horizontal nanowires spaced apart from the first vertical stack of horizontal nanowires, the third vertical stack of horizontal nanowires having the second number of nanowires.

6 . An integrated circuit structure, comprising:
a memory region having a first fin having a first height; and a logic region having a second fin spaced apart from the first fin, the second fin having a second height less than the first height, wherein a top surface of the second fin is at same level as a top surface of the first fin.

7 . The integrated circuit structure of claim 6 , wherein a ratio of the first height to the second height is about 4:3.

8 . The integrated circuit structure of claim 6 , further comprising a first gate structure portion over the first fin, a second gate structure portion over the second fin, and a gate cut between the first gate structure portion and the second gate structure portion.

9 . The integrated circuit structure of claim 8 , further comprising a dielectric gate plug in the gate cut.

10 . The integrated circuit structure of claim 6 , wherein the memory region further comprises a third fin spaced apart from the first fin, the third fin having the second height.

11 . A computing device, comprising:
a board; and a component coupled to the board, the component including an integrated circuit structure, comprising:
a memory region having a first vertical stack of horizontal nanowires having a first number of nanowires; and
a logic region having a second vertical stack of horizontal nanowires spaced apart from the first vertical stack of horizontal nanowires, the second vertical stack of horizontal nanowires having a second number of nanowires less than the first number of nanowires, wherein a top nanowire of the second vertical stack of horizontal nanowires is at same level as a top nanowire of the first vertical stack of horizontal nanowires.

12 . The computing device of claim 11 , further comprising:
a memory coupled to the board.

13 . The computing device of claim 11 , further comprising:
a communication chip coupled to the board.

14 . The computing device of claim 11 , wherein the component is a packaged integrated circuit die.

15 . The computing device of claim 11 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.

16 . A computing device, comprising:
a board; and a component coupled to the board, the component including an integrated circuit structure, comprising:
a memory region having a first fin having a first height; and
a logic region having a second fin spaced apart from the first fin, the second fin having a second height less than the first height, wherein a top surface of the second fin is at same level as a top surface of the first fin.

17 . The computing device of claim 16 , further comprising:
a memory coupled to the board.

18 . The computing device of claim 16 , further comprising:
a communication chip coupled to the board.

19 . The computing device of claim 16 , wherein the component is a packaged integrated circuit die.

20 . The computing device of claim 16 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.

Assignees

• Intel Corp

Inventors

• Mehandru Rishabh
• Weber Cory
• Ong Clifford
• Yemenicioglu Sukru
• Ghani Tahir
• Greene Brian

Classifications

• H10D84/83

  of only insulated-gate FETs [IGFET] · CPC title

• H10D62/121

  oriented parallel to substrates · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/43

  having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels · CPC title

• H10D30/014

  of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors · CPC title