Electronic device comprising transistors

Patent metadata

Field	Value
Publication number	US-12501643-B2
Application number	US-202217826706-A
Country	US
Kind code	B2
Filing date	May 27, 2022
Priority date	Jun 4, 2021
Publication date	Dec 16, 2025
Grant date	Dec 16, 2025

Abstract

An electronic device including semiconductor region located on a gallium nitride layer, two electrodes, located on either side of and insulated from the semiconductor region, the electrodes partially penetrating into the gallium nitride layer, and two lateral MOS transistors formed inside and on top of the semiconductor region.

First claim

The invention claimed is:

1 . Electronic device comprising:
a semiconductor region located on a gallium nitride layer and partially penetrating into the gallium nitride layer; two electrodes, located on either side of and not in contact with the semiconductor region, the electrodes partially penetrating into the gallium nitride layer and being connected to the semiconductor region via a two-dimensional electron gas; and two lateral MOS transistors formed inside and on top of the semiconductor region and connected in series between the two electrodes.

2 . Device according to claim 1 , wherein each transistor is configured to control the flowing of an electric current between one of said electrodes and one or a plurality of second electrodes supported by the semiconductor region.

3 . Device according to claim 2 , wherein a drain region of each transistor is coupled, via a two-dimensional electrode gas, to one of said electrodes.

4 . Device according to claim 3 , further comprising one or a plurality of conductive regions contacting the drain regions of the transistors and partially penetrating into the gallium nitride layer.

5 . Device according to claim 4 , comprising exactly two conductive regions coating opposite sides of the semiconductor region located in front of said electrodes and a single second electrode located between the transistors.

6 . Device according to claim 4 , comprising exactly two conductive regions comprising conductive vias located on either side of the semiconductor region and a single second electrode located between the transistors.

7 . Device according to claim 4 , comprising a single conductive region comprising a conductive via crossing the semiconductor region and exactly two second electrodes located on either side of the transistors.

8 . Device according to claim 2 , wherein the semiconductor region partially penetrates into the gallium nitride layer.

9 . Device according to claim 1 , wherein each transistor comprises a gate region located vertically in line with a channel region located between source and drain regions formed in the semiconductor region.

10 . Device according to claim 9 , wherein the source regions of the transistors are doped with a first conductivity type and separated by a well formed in the semiconductor region and doped with a second conductivity type, opposite to the first conductivity type.

11 . Device according to claim 1 , wherein a lower portion of the semiconductor region is insulated from the gallium nitride layer.

12 . Device according to claim 1 , wherein the first electrodes are intended to be taken to a same potential.

13 . Device according to claim 1 , wherein the semiconductor region is made of a material different from that of the gallium nitride layer, preferably of silicon or of silicon carbide.

14 . Method of forming a device according to claim 1 , the method comprising the steps of:
a) forming a trench inside of the gallium nitride layer; b) forming the first electrodes on either side of the trench; c) filling the trench with the semiconductor region; d) forming the MOS transistors.

15 . Method according to claim 14 , wherein each transistor is configured to control the flowing of an electric current between one of said electrodes and one or a plurality of second electrodes supported by the semiconductor region, and further comprising, after step d) a step of forming the second electrode.

16 . Method according to claim 14 , wherein each transistor is configured to control the flowing of an electric current between one of said electrodes and one or a plurality of second electrodes supported by the semiconductor region and wherein the drain region of each transistor is coupled, via a two-dimensional electrode gas, to one of said electrodes, further comprising one or a plurality of conductive regions contacting the drain regions of the transistors and partially penetrating into the gallium nitride layer, wherein the conductive regions are formed at step b).

Assignees

• Commissariat A Ienergie Atomique Et Aux Energies Alternatives
• Commissariat Energie Atomique

Inventors

• Escoffier René
• Mohamad Blend

Classifications

• H10D84/151

  LDMOS having built-in components · CPC title

• H10D64/118

  Electrodes comprising insulating layers having particular dielectric or electrostatic properties, e.g. having static charges · CPC title

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title

• H10D30/015

  of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT · CPC title

• H10D1/40

  Resistors · CPC title