Method for forming a transistor with a conductivity doped base structure

Patent metadata

Field	Value
Publication number	US-12501634-B2
Application number	US-202217929877-A
Country	US
Kind code	B2
Filing date	Sep 6, 2022
Priority date	Sep 6, 2022
Publication date	Dec 16, 2025
Grant date	Dec 16, 2025

Abstract

A method for forming a transistor with an emitter, intrinsic base, and collector. The base includes a semiconductor layer doped with a conductivity dopant to provide for a lower resistivity path to the intrinsic base. After the formation of a layer over a substrate, an emitter window opening is formed in the layer. The semiconductor layer is formed through the opening by a deposition process. A portion of the semiconductor layer is then removed. An emitter electrode is formed that includes at least a portion located in the opening. A remaining portion of the semiconductor layer is in a conductive path to the intrinsic base.

First claim

What is claimed is:

1 . A method for forming a transistor, the method comprising:
forming a collector of the transistor; forming an intrinsic base of the transistor; forming a first layer over a substrate; forming a first opening in the first layer; forming a first semiconductor layer doped with a conductivity dopant after forming the first opening, wherein forming the first semiconductor layer includes depositing semiconductor material on surfaces through the first opening by a material deposition process after forming the first opening, and wherein the first semiconductor layer is characterized as a silicon germanium layer; removing a first portion of the first semiconductor layer after forming the first semiconductor layer, wherein at least a second portion of the first semiconductor layer remains after removing the first portion; and forming an emitter electrode after removing the first portion, wherein the emitter electrode includes at least a portion located in the first opening, and wherein the second portion of the first semiconductor layer is in a conductive path to the intrinsic base of the transistor.

2 . The method of claim 1 , wherein the first portion of the first semiconductor layer is located directly over the intrinsic base of the transistor.

3 . The method of claim 1 , wherein removing the first portion forms a second opening, wherein forming the intrinsic base includes forming at least a portion of the intrinsic base in the second opening after removing the first portion.

4 . The method of claim 1 , further comprising:
forming a base silicide structure, wherein the second portion of the first semiconductor layer is in a conductive path between the intrinsic base and the base silicide structure.

5 . A method for forming a transistor, the method comprising:
forming a collector of the transistor; forming an intrinsic base of the transistor; forming a first layer over a substrate, wherein the first layer is characterized as a semiconductor layer; forming a first opening in the first layer; forming a first semiconductor layer doped with a conductivity dopant after forming the first opening, wherein forming the first semiconductor layer includes depositing semiconductor material on surfaces through the first opening by a material deposition process after forming the first opening; removing a first portion of the first semiconductor layer after forming the first semiconductor layer, wherein at least a second portion of the first semiconductor layer remains after removing the first portion, and wherein at least a portion of the second portion is contacting an underside surface of the first layer; and forming an emitter electrode after removing the first portion, wherein the emitter electrode includes at least a portion located in the first opening, and wherein the second portion of the first semiconductor layer is in a conductive path to the intrinsic base of the transistor.

6 . The method of claim 5 , wherein removing the first portion of the first semiconductor layer includes utilizing an etching process that is selective to a material of the first layer.

7 . The method of claim 1 , wherein the intrinsic base is located in a silicon germanium layer, a silicon layer is formed on the silicon germanium layer, wherein the first semiconductor layer is formed on the silicon layer.

8 . The method of claim 1 , wherein the first semiconductor layer is formed on a silicon monocrystalline portion of the substrate.

9 . The method of claim 1 , further comprising:
forming a second layer over the substrate prior to forming the first layer; removing at least a portion of the second layer through the first opening, wherein at least a portion of the first semiconductor layer is formed at a location where at least a portion of the second layer was removed.

10 . The method of claim 9 , wherein a first portion of the at least the portion of the second layer is located directly below the first opening in the first layer, and a second portion of the at least the portion of the second layer is located directly below the first layer lateral to the first opening, and wherein at least a portion of the second portion of the first semiconductor layer is located directly underneath the first layer lateral to the first opening.

11 . The method of claim 9 , wherein the second layer is patterned prior to forming the first layer.

12 . The method of claim 9 , wherein removing the at least the portion of the second layer through the first opening forms a second opening, and wherein forming the first semiconductor layer includes forming the first semiconductor layer on exposed surfaces of the second opening.

13 . The method of claim 12 , further comprising:
forming a silicon layer on the first semiconductor layer, including forming the silicon layer in portions of the second opening.

14 . The method of claim 1 , wherein:
the first layer is a dielectric layer.

15 . The method of claim 14 , wherein the first layer includes nitride.

16 . The method of claim 1 , wherein the first layer is characterized as a semiconductor layer, and wherein the second portion is in a conductive base path between the intrinsic base and the first layer.

17 . The method of claim 1 , wherein the collector is formed in the substrate.

18 . A method for forming a transistor, the method comprising:
forming a collector of the transistor in a substrate; forming an intrinsic base of the transistor; forming a first layer over the substrate; forming a first opening in the first layer; forming a silicon germanium (SiGe) layer doped with a conductivity dopant after the forming the first opening, wherein forming the SiGe layer includes epitaxially depositing semiconductor material on surfaces through the first opening by a material deposition process after forming the first opening; removing a first portion of the SiGe layer after forming the SiGe layer, wherein at least a second portion of the SiGe layer remains after removing the first portion of the SiGe layer; and forming an emitter electrode after removing the first portion of the SiGe layer, wherein the emitter electrode includes at least a portion located in the first opening, and wherein the second portion of the SiGe layer is in a conductive path to the intrinsic base of the transistor.

19 . The method of claim 18 , further comprising:
forming a second layer over the substrate prior to forming the first layer; and removing at least a portion of the second layer through the first opening, wherein at least a portion of the SiGe layer is formed at a location where the at least the portion of the second layer was removed.

Assignees

• Nxp Usa Inc

Inventors

• John Jay Paul
• Kirchgessner James Albert
• Radic Ljubo
• Donkers Johannes Josephus Theodorus Marinus

Classifications

• H10D10/861

  having an emitter region comprising one or more non-monocrystalline elements of Group IV, e.g. amorphous silicon · CPC title

• H10D10/021 Primary

  of heterojunction BJTs [HBT] · CPC title

• H10D64/62

  Electrodes ohmically coupled to a semiconductor · CPC title

• H10D62/177

  Base regions of bipolar transistors, e.g. BJTs or IGBTs · CPC title

• H10D62/138

  Pedestal collectors · CPC title