Clock interpolation system for eye-centering

Patent metadata

Field	Value
Publication number	US-12500583-B2
Application number	US-202217889892-A
Country	US
Kind code	B2
Filing date	Aug 17, 2022
Priority date	Jun 2, 2022
Publication date	Dec 16, 2025
Grant date	Dec 16, 2025

Abstract

Embodiments herein relate to a clock interpolation system. The system may be configured to identify, at a change in logical state of a recovered clock signal, a logical state of a first signal when the first signal is delayed by a delay value. The system may be further configured to identify, at a change in logical state of a second signal, a logical state of the clock signal when the clock signal is delayed by the delay value. Based on the two identifications, the delay value and/or a timing of the clock signal may be adjusted. Other embodiments may be described and/or claimed.

First claim

What is claimed is:

1 . A clock interpolation system comprising:
a clock processing module to generate, based on one or more received clock signals, a recovered clock signal, a first signal related to a left edge of the recovered clock signal, and a second signal related to a right edge of the recovered clock signal; a monitor delay module to:
apply a first delay to a recovered clock signal to generate a delayed recovered clock signal; and
apply the first delay to the first signal to generate a delayed first signal; and
a sampler to:
identify a first logical value related to a logical state of the delayed first signal at a logical change of the recovered clock signal;
identify a second logical value related to a logical state of the delayed clock signal at a logical change of the second signal; and
facilitate, based on the identified first and second logical values, a change to a value of the first delay.

2 . The clock interpolation system of claim 1 , wherein the clock processing module is to generate the recovered clock signal based on application of a second delay to a clock signal of the one or more received clock signals.

3 . The clock interpolation system of claim 2 , wherein the sampler is further to facilitate a change to the recovered clock signal based on a change in a value of the second delay.

4 . The clock interpolation system of claim 3 , wherein if the first logical value is “0” and the second logical value is “1,” then the change in the second delay includes increasing the second delay.

5 . The clock interpolation system of claim 3 , wherein if the first logical value is “0” and the second logical value is “1,” then the change in the second delay includes decreasing the second delay.

6 . The clock interpolation system of claim 1 , wherein the logical change of the recovered clock signal is a rising edge of the recovered clock signal.

7 . The clock interpolation system of claim 1 , wherein the logical change of the second signal is a rising edge of the second signal.

8 . The clock interpolation system of claim 1 , further comprising a multiplexer to:
receive, from the clock processing module, the recovered clock signal and the second signal; and selectively output one of the recovered clock signal and the second signal to the sampler.

9 . The clock interpolation system of claim 1 , further comprising a multiplexer to:
receive, from the clock processing module, the recovered clock signal and the first signal; and selectively output one of the recovered clock signal and the second signal to the monitor delay module.

10 . An electronic device comprising:
transmit circuitry to transmit a set of one or more clock signals and one or more data signals; receive circuitry to identify a set of one or more received clock signals and one or more received data signals; and a clock interpolation system to:
identify, based on the set of one or more received clock signals, a recovered clock signal, a first signal that is based on a beginning of a logical data eye that is related to the set of one or more received clock signals, and a second signal that is based on an end of the logical data eye;
apply a first delay value to the first signal to generate a delayed first signal;
identify a first logical value that is related to a value of the delayed first signal at a logical change of the recovered clock signal;
apply the first delay value to the recovered clock signal to generate a delayed recovered clock signal;
identify a second logical value that is related to a value of the delayed recovered clock signal at a logical change of the second signal; and
change, based on the first logical value and the second logical value, the first delay value or a timing of the recovered clock signal.

11 . The electronic device of claim 10 , wherein the clock interpolation system is an element of the transmit circuitry.

12 . The electronic device of claim 10 , wherein the clock interpolation system is an element of the receive circuitry.

13 . The electronic device of claim 10 , wherein the recovered clock signal is a QCLK signal.

14 . The electronic device of claim 10 , wherein the first signal is a QCLK_LEFT_EDGE signal.

15 . The electronic device of claim 10 , wherein the second signal is a QCLK_RIGHT_EDGE signal.

16 . The electronic device of claim 10 , wherein if the first logical value is “1” and the second logical value is “1,” then the first delay value is increased.

17 . The electronic device of claim 10 , wherein if the first logical value is “0” and the second logical value is “0,” then the first delay value is decreased.

18 . One or more non-transitory computer-readable media comprising instructions that, upon execution by one or more processors of an electronic device, are to cause a clock interpolation system of the electronic device to:
identify, based on a set of one or more received clock signals, a recovered clock signal, a first signal that is based on a beginning of a logical data eye that is related to the set of one or more received clock signals, and a second signal that is based on an end of the logical data eye; apply a first delay value to the first signal to generate a delayed first signal; identify a first logical value that is related to a value of the delayed first signal at a logical change of the recovered clock signal; apply the first delay value to the recovered clock signal to generate a delayed recovered clock signal; identify a second logical value that is related to a value of the delayed recovered clock signal at a logical change of the second signal; and change, based on the first logical value and the second logical value, the first delay value or a timing of the recovered clock signal.

19 . The one or more non-transitory computer-readable media of claim 18 , wherein the first signal is related to an earliest error-free value of the set of one or more received clock signals.

20 . The one or more non-transitory computer-readable media of claim 18 , wherein the second signal is related to a latest error-free value of the set of one or more received clock signals.

Assignees

• Intel Corp

Inventors

• Desai Jayen
• Pasdast Gerald
• Wang Peipei
• Das Sharma Debendra

Classifications

• G06F1/12

  Synchronisation of different clock signals {provided by a plurality of clock generators} · CPC title

• H03K2005/00013

  Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse · CPC title

• H03K5/13 Primary

  Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals · CPC title