Wafer-level package sensor device

Patent metadata

Field	Value
Publication number	US-12499343-B2
Application number	US-202318524353-A
Country	US
Kind code	B2
Filing date	Nov 30, 2023
Priority date	Dec 15, 2022
Publication date	Dec 16, 2025
Grant date	Dec 16, 2025

Abstract

A wafer-level package sensor device including a capacitive sensor, a controller which is electrically conductively connected to the sensor, wherein the capacitive sensor is formed by partially overlapping redistribution layer tracks of the wafer-level package sensor device formed in different planes, and multiple contact surfaces connected to the controller, which are configured to electrically couple to a chip card module carrier using a flip-chip connection.

First claim

The invention claimed is:

1 . A wafer-level package sensor device, comprising:
a capacitive sensor; a controller which is electrically conductively connected to the sensor, wherein the capacitive sensor is formed by partially overlapping redistribution layer tracks of the wafer-level package sensor device formed in different planes; and multiple contact surfaces which are connected to the controller and configured to electrically couple to a chip-card module carrier using a flip-chip connection, wherein the multiple contact surfaces and a sensor surface of the capacitive sensor are exposed on a same side of the wafer-level package sensor device.

2 . The wafer-level package sensor device as claimed in claim 1 ,
wherein the sensor and the controller are arranged vertically stacked in the wafer-level package sensor device.

3 . The wafer-level package sensor device as claimed in claim 1 ,
wherein the multiple contact surfaces are formed as part of the redistribution layer tracks.

4 . The wafer-level package sensor device as claimed in claim 1 ,
wherein the wafer-level package sensor device is free of passive components.

5 . A chip card module, comprising:
a wafer-level package sensor device as claimed in claim 1 ; and a secure element chip, which is electrically conductively connected to the capacitive sensor.

6 . The chip card module as claimed in claim 5 , further comprising:
a carrier with a circuit which is connected to a first set of contact pads and to a second set of contact pads.

7 . The chip card module as claimed in claim 6 ,
wherein the secure element chip is connected to the first set of contact pads, and the wafer-level package sensor device is connected to the second set of contact pads.

8 . The chip card module as claimed in claim 6 ,
wherein the secure element chip and the wafer-level package sensor device are arranged laterally next to each other.

9 . The chip card module as claimed in claim 6 ,
wherein the secure element chip and the wafer-level package sensor device are connected to the carrier using flip-chip connections.

10 . The chip card module as claimed in claim 5 , further comprising:
a contact surface array, which is connected to the secure element chip and configured for contact-based operation of the chip card module; and/or an antenna which is connected to the secure element chip and configured for contactless operation of the chip card module.

11 . A method for forming a wafer-level package sensor device, the method comprising:
forming a capacitive sensor by forming partially overlapping redistribution layer tracks of the wafer-level package sensor device in different planes; connecting a controller to the sensor in an electrically conductive manner; and forming multiple contact surfaces which are connected to the controller and configured to electrically couple to a chip card module carrier using a flip-chip connection, wherein the multiple contact surfaces and a sensor surface of the capacitive sensor are exposed on the same side of the wafer-level package sensor device.

12 . The method as claimed in claim 11 ,
wherein the sensor and the controller are arranged vertically stacked in the wafer-level package sensor device.

13 . The method as claimed in claim 11 ,
wherein the multiple contact surfaces are formed together with some of the redistribution layers.

14 . The method as claimed in claim 11 , further comprising:
forming a plurality of wafer-level package sensor devices as parts of a reconstituted wafer; and separating the reconstituted wafer into a plurality of wafer-level package sensor devices.

15 . A method for forming a chip card module, comprising:
forming a wafer-level package sensor device as claimed in claim 11 ; and connecting a secure element chip to the capacitive sensor in an electrically conductive manner.

16 . The method as claimed in claim 15 , further comprising:
providing a carrier with a circuit which is connected to a first set of contact pads and to a second set of contact pads.

17 . The method as claimed in claim 16 , further comprising:
connecting the secure element chip to the first set of contact pads; and connecting the wafer-level package sensor device to the second set of contact pads.

18 . The method as claimed in claim 15 , further comprising:
providing a contact surface array which is connected to the secure element chip and configured for contact-based operation of the chip card module; and/or providing an antenna which is connected to the secure element chip and configured for contactless operation of the chip card module.

Assignees

• Infineon Technologies Ag

Inventors

• Püschner Frank
• Pavier Mark
• Ebersberger Bernd

Classifications

• G06K19/0718

  the sensor being of the biometric kind, e.g. fingerprint sensors (fingerprint sensors in general G06V40/13; biometric access-control systems in general, see G07C9/00) · CPC title

• G06K19/07775

  the antenna being on-chip · CPC title

• G06V40/1306 Primary

  non-optical, e.g. ultrasonic or capacitive sensing · CPC title

• G06K19/07756 Primary

  the connection being non-galvanic, e.g. capacitive · CPC title