Memory module, system including the same, and operation method of memory module

Patent metadata

Field	Value
Publication number	US-12499072-B2
Application number	US-202217715158-A
Country	US
Kind code	B2
Filing date	Apr 7, 2022
Priority date	Jul 23, 2021
Publication date	Dec 16, 2025
Grant date	Dec 16, 2025

Abstract

A memory module includes a device memory configured to store data and including a first memory area and a second memory area, and a controller including an accelerator circuit. The controller is configured to control the device memory, transmit a command to exclude the first memory area from the system memory map to a host processor in response to a mode change request, and modify a memory configuration register to exclude the first memory area from the memory configuration register. The accelerator circuit is configured to use the first memory area to perform an acceleration operation.

First claim

What is claimed is:

1 . A memory module, comprising:
a device memory configured to store data, the device memory including a first memory area and a second memory area; and a controller including an accelerator circuit, wherein the controller is configured to
control the device memory,
transmit a command to exclude the first memory area from a system memory map to a host processor, in response to a mode change request, and
modify a memory configuration register to exclude the first memory area from the memory configuration register,
wherein the accelerator circuit is configured to use the first memory area to perform an acceleration operation, wherein the mode change request includes an application program switching from a user mode to a kernel mode, and wherein a unit of the first memory area is defined as a channel including a plurality of sub-channels, and wherein at least one delay device is disposed between the sub-channels.

2 . The memory module of claim 1 , wherein the first memory area is excluded from the system memory map by hot-plugging out the first memory area.

3 . The memory module of claim 1 , wherein the controller includes the memory configuration register, which includes at least one memory address identifying the first memory area.

4 . The memory module of claim 3 , wherein the controller stores data necessary for the acceleration operation in the first memory area, and performs the acceleration operation using the data.

5 . The memory module of claim 1 , wherein the first memory area is changed from being used for a system memory to be used exclusively for an acceleration operation, and the second memory area is used for a system memory.

6 . A system, comprising:
a first memory including a first memory area and a second memory area different from the first memory area; a controller configured to directly communicate with the first memory; a second memory; and a processor configured to directly communicate with the second memory and communicate with the controller through a heterogeneous computing interface, wherein the first memory is configured to operate as a system memory in which the controller and the processor are each configured to store data in each of the first memory area and the second memory area, and configured to operate as a dedicated memory in which only the controller is configured to store data to each of the first memory area and the second memory area, wherein the first memory operates as dedicated memory in response to the processor excluding the first memory area of the first memory from a system memory map, and the controller excluding the first memory area from a memory configuration register, and wherein when the first memory operates as dedicated memory, the first memory area is used exclusively for an acceleration operation executed by the controller.

7 . The system of claim 6 , wherein the controller is configured to move data stored in the first memory area to the second memory area.

8 . The system of claim 7 , wherein the controller is configured to determine whether residual capacity of the first memory area is sufficient to perform the acceleration operation, and when it is determined that the residual capacity of the first memory area is insufficient, the controller is configured to move the data stored in the first memory area to the second memory area.

9 . The system of claim 7 , wherein, after the data stored in the first memory area moves to the second memory area, the processor is configured to exclude the first memory area from the system memory map in response to a request from the controller.

10 . The system of claim 7 , wherein the controller includes the memory configuration register, which includes at least one memory address identifying the first memory area.

11 . The system of claim 6 , wherein the controller and the processor communicate with each other through a COMPUTE EXPRESS LINK (CXL) interface.

12 . The system of claim 6 , wherein the controller and the first memory communicate with each other through a dual data rate (DDR) interface.

13 . A method of operating a memory module, the method comprising:
receiving, by a controller, a first mode change request for changing an operation mode of a first memory from a system memory in which the controller and a processor are each configured to store data in each of a first memory area and a second memory area included in the first memory, to a dedicated memory in which only the controller is configured to store data to each of the first memory area and the second memory area; transmitting, by the controller, a command to exclude the first memory area from a system memory map, in response to the first mode change request; and modifying, by the controller, a memory configuration register to exclude the first memory area from the memory configuration register, wherein when the first memory operates as dedicated memory, the first memory area is used exclusively for an acceleration operation executed by the controller.

14 . The method of claim 13 , further comprising:
storing, by the controller, data necessary for the acceleration operation in the first memory area; and performing, by the controller, an acceleration operation using the data.

15 . The method of claim 14 , further comprising:
receiving, by the controller, a second mode change request for changing the operation mode of the first memory back to system memory after the acceleration operation is completed; and modifying, by the controller, the memory configuration register to include the first memory area when the first memory area is included in the system memory map in response to the second mode change request.

16 . The system of claim 6 , wherein the controller and the first memory are colocated on a memory module and the system memory map is stored external to the memory module.

17 . The system of claim 6 , wherein the controller is configured to adjust a size of the first memory area in response to a calculated memory capacity required to perform the acceleration operation.

18 . The method of claim 13 , wherein the controller and the first memory are colocated on the memory module and the system memory map is stored external to the memory module.

19 . The method of claim 13 , further comprising:
adjusting, by the controller, a size of the first memory area in response to a calculated memory capacity required to perform the acceleration operation.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Jonggeon
• So Jinin
• Kwon Yongsuk
• Kim Kyungsoo
• Yun Ilkwon
• Cho Jeonghyeon

Classifications

• G06F13/409

  Mechanical coupling (back panels H05K7/1438) · CPC title

• G06F13/1668

  Details of memory controller · CPC title

• G06F9/30189

  according to execution mode, e.g. mode flag · CPC title

• G06F13/387

  for adaptation of different data processing systems to different peripheral devices, e.g. protocol converters for incompatible systems, open system · CPC title

• G06F12/063

  for I/O modules, e.g. memory mapped I/O (I/O protocol G06F13/42) · CPC title