Architecture for dynamic transformation of memory configuration

Patent metadata

Field	Value
Publication number	US-10877693-B2
Application number	US-201816024637-A
Country	US
Kind code	B2
Filing date	Jun 29, 2018
Priority date	Jun 29, 2018
Publication date	Dec 29, 2020
Grant date	Dec 29, 2020

Abstract

One embodiment provides an apparatus. The apparatus includes first memory controller circuitry to control read and/or write access to first memory circuitry via a first conductive bus. The apparatus includes second memory controller circuitry to control read and/or write access to second memory circuitry via a second conductive bus. The apparatus includes power control circuitry coupled to the first memory controller circuitry and the second memory controller circuitry. The power control circuitry transfers data from the second memory circuitry with the second memory controller circuitry via the second conductive bus to the first memory circuitry with the first memory controller circuitry via the first conductive bus. The power control circuitry powers down the second memory circuitry after the transfer of the data from the second memory circuitry to the first memory circuitry. The power control circuitry decreases power consumption of the apparatus and may increase batter life of the apparatus.

First claim

What is claimed is:

1. An apparatus comprising:
first memory controller circuitry configured to control read and/or write access to first memory circuitry via a first conductive bus;
second memory controller circuitry configured to control read and/or write access to second memory circuitry via a second conductive bus; and
power control circuitry coupled to the first memory controller circuitry and the second memory controller circuitry, the power control circuitry configured to:
cause the first memory controller circuitry to:
transfer one or more least recently used (LRU) memory pages from the first memory circuitry to a persistent storage device; and
consolidate a plurality of memory pages remaining in the first memory circuitry to sequential locations within the first memory circuitry to provide a plurality of first memory segments;

cause the second memory controller circuitry to:
transfer one or more least recently used (LRU) memory pages from the second memory circuitry to the persistent storage device; and
consolidate a plurality of memory pages remaining in the second memory circuitry to sequential locations within the second memory circuitry to provide a plurality of second memory segments;
transfer the plurality of second memory segments from the second memory circuitry to the first memory circuitry via the second conductive bus, the first memory controller circuitry, and the first conductive bus; and

power down the second memory circuitry responsive to the second memory controller circuitry successfully completing the transfer of the second plurality of memory segments to the first memory circuitry.

2. The apparatus of claim 1 , wherein the first memory circuitry includes a first plurality of memory packages, wherein the first conductive bus includes a first plurality of channels to couple the first memory controller circuitry to the first plurality of memory packages; and
wherein the second conductive bus includes a second plurality of channels to couple the second memory controller circuitry to the second plurality of memory packages.

3. The apparatus of claim 2 , wherein the power control circuitry is configured to power down the second memory circuitry by powering down the second plurality of memory controllers and the second plurality of memory packages.

4. The apparatus of claim 1 , wherein to transfer the second plurality of memory segments from the second memory circuitry to the first memory circuitry, the power control circuitry is further configured to:
transfer the second plurality of memory segments, each of the second plurality of memory segments including a plurality of dynamic random-access memory (“DRAM”) pages of memory within the second memory circuitry to DRAM pages of memory within the first memory circuitry.

5. The apparatus of claim 1 , wherein, while the second memory circuitry is powered down, the second memory controller circuitry is configured to route new traffic to locations within the first memory circuitry if new traffic maps to locations within the second memory circuitry.

6. The apparatus of claim 1 , the power control circuitry is configured to further:
receive a command to power up the second memory circuitry; and
return transferred data from the first memory circuitry to the second memory circuitry responsive to receipt of the command to power up the second memory circuitry.

7. The apparatus of claim 1 , wherein to power down the second memory circuitry the power control circuitry is further configured to perform one or more of:
cease clock signal transmission to the second memory circuitry over the second conductive bus;
remove power to the second memory circuitry;
disable automated self-refresh operations for the second memory circuitry; or
at least partially remove power to the second memory controller circuitry.

8. The apparatus of claim 1 , wherein to power down the second memory circuitry, the power control circuitry is further configured to:
power down the second memory controller circuitry.

9. The apparatus of claim 1 , the power control circuitry to further:
read a power control register; and
cause the second memory controller circuitry to transfer the second plurality of memory segments from the second memory circuitry to the first memory circuitry responsive to a defined bit configuration stored in the power control register.

10. The apparatus of claim 9 , wherein the power control register is accessible by an operating system executed by a processor.

11. A non-transitory computer-readable device having instructions to, when executed by power control circuitry, cause the power control circuitry to perform operations, comprising:
receive an instruction to transfer memory pages from a second memory circuitry to a first memory circuitry via a first memory controller circuitry communicatively coupled to the first memory circuitry and second memory controller circuitry communicatively coupled to the second memory circuitry;
cause first memory controller circuitry to:
transfer one or more least recently used (LRU) memory pages from the first memory circuitry to a persistent storage device; and
consolidate a plurality of memory pages remaining in the first memory circuitry to sequential locations within the first memory circuitry to provide a plurality of first memory segments;

cause second memory controller circuitry to:
transfer one or more least recently used (LRU) memory pages from the second memory circuitry to the persistent storage device; and
consolidate a plurality of memory pages remaining in the second memory circuitry to sequential locations within the second memory circuitry to provide a plurality of second memory segments;

cause the first memory controller circuitry and the second memory controller circuitry to transfer the plurality of second memory segments from the second memory circuitry to the first memory circuitry;
and
decrease power applied to the second memory circuitry responsive to the second memory controller circuitry successfully completing the transfer of the second plurality of memory segments to the first memory circuitry.

12. The non-transitory computer-readable device of claim 11 , wherein decrease power applied to the second memory circuitry includes one or more of:
cease clock signal transmission to the second memory circuitry over second channels;
remove power to the second memory circuitry;
disable automated self-refresh operations for the second memory circuitry; or
at least partially remove power to the second memory controller circuitry.

13. The non-transitory computer-readable device of claim 11 , further comprising:
receive, by the power control circuitry, a command to re-apply power to the second memory circuitry; and
cause, by the power control circuitry, a transfer of at least a portion of the second plurality of memory segments from the first memory circuitry to the second memory circuitry, responsive to receipt of the command to re-apply power to the second memory circuitry.

14. The non-transitory computer-readable device of claim 11 , wherein the instructions that cause the power control circuitry to receive an instruction to transfer memory pages from second memory circuitry data to first memory circuitry via first channels from second memory circuitry via the second channels further cause the power control circuitry to:
read bits from a power control register that stores configuration settings for the first memory circuitry and the second memory circuitry.

15. A system comprising:
a processor;
at least one memory controller configured to:
control read and

Assignees

• Intel Corp

Inventors

• Bonen Nadav
• Mandelblat Julius
• Sucher Nir

Classifications

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F13/4068

  Electrical coupling · CPC title

• G06F13/1668

  Details of memory controller · CPC title

• G06F3/0673

  Single storage device · CPC title

• G06F3/0659 Primary

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title