Systems, methods, and apparatus for accessing data in versions of memory pages

Patent metadata

Field	Value
Publication number	US-12499054-B2
Application number	US-202217986889-A
Country	US
Kind code	B2
Filing date	Nov 14, 2022
Priority date	Aug 22, 2022
Publication date	Dec 16, 2025
Grant date	Dec 16, 2025

Abstract

An apparatus may include at least one memory, and at least one processor configured to determine an accessibility of a first version of a page, wherein the first version of the page may be stored in the at least one memory, and perform, based on the accessibility of the first version of the page, an access of at least a portion of a second version of the page, wherein the second version of the page is stored in the at least one memory. The accessibility of the first version of the page may be based on an erase operation of the first version of the page. The access of the at least a portion of the second version of the page may include an access of a cache line of the second version of the page.

First claim

The invention claimed is:

1 . A method comprising:
determining an accessibility of a first version of a page, wherein the first version of the page is stored in at least one memory; and accessing, based on the accessibility of the first version of the page, at least a portion of a second version of the page, wherein the second version of the page is stored in the at least one memory, wherein a part of the first version of the page is the same as a part of the second version of the page and a bitmap data structure is used to determine that the part of the first version of the page and the part of the second version are the same, the bitmap data structure indicating a status of one or more cache lines of the second version of the page and one or more cache lines of the first version of the page.

2 . The method of claim 1 , further comprising determining a modification status of a portion of the first version of the page, wherein the accessing the at least a portion of the second version of the page comprises accessing a portion of the second version of the page corresponding to the portion of the first version of the page.

3 . An apparatus comprising:
at least one memory; and at least one processor configured to: determine an accessibility of a first version of a page, wherein the first version of the page is stored in the at least one memory; and perform, based on the accessibility of the first version of the page, an access of at least a portion of a second version of the page, wherein the second version of the page is stored in the at least one memory, wherein a part of the first version of the page is the same as a part of the second version of the page and a bitmap data structure is used to determine that the part of the first version of the page and the part of the second version are the same, the bitmap data structure indicating a status of one or more cache lines of the second version of the page and one or more cache lines of the first version of the page.

4 . The apparatus of claim 3 , wherein the accessibility of the first version of the page is based on an erase operation of the first version of the page.

5 . The apparatus of claim 3 , wherein the accessibility of the first version of the page is based on an amount of accesses of the first version of the page.

6 . The apparatus of claim 5 , wherein the accessibility of the first version of the page is further based on an amount of accesses of the second version of the page.

7 . The apparatus of claim 3 , wherein the access of the at least a portion of the second version of the page comprises an access of a cache line of the second version of the page.

8 . The apparatus of claim 3 , wherein the access of the at least a portion of the second version of the page is based on a modification status of the first version of the page.

9 . The apparatus of claim 8 , wherein:
the access of the at least a portion of the second version of the page comprises an access of a portion of the second version of the page; and the modification status of the first version of the page is based on a modification status of a portion of the first version of the page corresponding to the portion of the second version of the page.

10 . The apparatus of claim 9 , wherein:
the portion of the first version of the page comprises a cache line of the first version of the page; and the portion of the second version of the page comprises a cache line of the second version of the page corresponding to the cache line of the first version of the page.

11 . The apparatus of claim 3 , wherein the at least one processor is configured to track a modification status of the at least a portion of the second version of the page.

12 . The apparatus of claim 3 , wherein the access of the at least a portion of the second version of the page comprises a read operation.

13 . The apparatus of claim 3 , wherein the at least one processor is configured to:
store, in a first superblock, the first version of the page; and store, in a second superblock, the second version of the page.

14 . The apparatus of claim 3 , further comprising a cache configured to store the first version of the page, wherein the at least one processor is configured to track a modification status of the first version of the page.

15 . The apparatus of claim 14 , wherein the at least one processor is configured to evict the first version of the page based on the modification status of the first version of the page.

16 . The apparatus of claim 3 , wherein:
the apparatus comprises a storage device; and the at least one memory comprises at least one storage media.

17 . The apparatus of claim 16 , wherein the storage device is configured to operate in a coherent memory mode.

18 . An apparatus comprising:
at least one memory; and at least one processor configured to:
store a first version of a page in at least one memory;
store a second version of the page in the at least one memory; and
track a modification status of at least a portion of the first version of the page, wherein a part of the first version of the page is the same as a part of the second version of the page and a bitmap data structure is used to determine that the part of the first version of the page and the part of the second version are the same, the bitmap data structure indicating a status of one or more cache lines of the second version of the page and one or more cache lines of the first version of the page.

19 . The apparatus of claim 18 , wherein the modification status of the at least a portion of the first version of the page comprises a modification status of a portion of the first version of the page.

20 . The apparatus of claim 19 , wherein the portion of the first version of the page comprises a cache line.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Zhang Da
• Yang Jing
• Zhang Tong
• Pei Shuyi
• Pitchumani Rekha

Classifications

• G06F2212/1024

  Latency reduction · CPC title

• G06F12/0804

  with main memory updating (G06F12/0806 takes precedence) · CPC title

• G06F2212/7201

  Logical to physical mapping or translation of blocks or pages · CPC title

• G06F3/064

  Management of blocks · CPC title

• G06F12/0292

  using tables or multilevel address translation means (G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10) · CPC title