Method for supporting erasure code data protection with embedded PCIE switch inside FPGA+SSD

Patent metadata

Field	Value
Publication number	US-10635609-B2
Application number	US-201816207080-A
Country	US
Kind code	B2
Filing date	Nov 30, 2018
Priority date	Mar 2, 2018
Publication date	Apr 28, 2020
Grant date	Apr 28, 2020

Abstract

A Peripheral Component Interconnect Express (PCIe) switch with Erasure Coding logic is disclosed. The PCIe switch may include an external connector to enable the PCIe switch to communicate with a processor and at least one connector to enable the PCIe switch to communicate with at least one storage device. The PCIe switch may include a Power Processing Unit (PPU) to handle configuration of the PCIe switch. The Erasure Coding logic may include an Erasure Coding Controller with circuitry to apply an Erasure Coding scheme to data stored on the storage device, and a snooping logic including circuitry to intercept a data transmission received at the PCIe switch and modify the data transmission responsive to the Erasure Coding scheme.

First claim

What is claimed is:

1. A Peripheral Component Interconnect Express (PCIe) switch with Erasure Coding logic, comprising:
an external connector to enable the PCIe switch to communicate with a processor;
at least one connector to enable the PCIe switch to communicate with at least one storage device;
a Power Processing Unit (PPU) to handle configuration of the PCIe switch;
an Erasure Coding Controller including circuitry to apply an Erasure Coding scheme to data stored on the at least one storage device; and
a snooping logic including circuitry to intercept a data transmission received at the PCIe switch and modify the data transmission responsive to the Erasure Coding scheme.

2. The PCIe switch with Erasure Coding logic according to claim 1 , wherein the Erasure Coding logic is drawn from a set including a Look-Aside Erasure Coding logic and a Look-Through Erasure Coding logic.

3. The PCIe switch with Erasure Coding logic according to claim 1 , wherein the at least one storage device include at least one Non-Volatile Memory Express (NVMe) Solid State Drive (SSD).

4. The PCIe switch with Erasure Coding logic according to claim 3 , further comprising a cache.

5. The PCIe switch with Erasure Coding logic according to claim 4 , wherein the snooping logic is operative to return a response to the data transmission from a host based at least in part on a data requested in the data transmission is present in the cache.

6. The PCIe switch with Erasure Coding logic according to claim 3 , wherein:
the PCIe switch is operative to detect a failed NVMe SSD of the at least one NVMe SSD; and
the Erasure Coding Controller is operative to handle the data transmission to account for the failed NVMe SSD.

7. The PCIe switch with Erasure Coding logic according to claim 3 , wherein:
the PCIe switch is operative to detect a new NVMe SSD; and
the Erasure Coding Controller is operative to use the new NVMe SSD as part of the Erasure Coding scheme.

8. The PCIe switch with Erasure Coding logic according to claim 3 ,
wherein the PCIe switch is operative to present itself as a single device to a host and to prevent downstream PCIe bus enumeration of the at least one NVMe SSD.

9. The PCIe switch with Erasure Coding logic according to claim 8 , wherein the PCIe switch is operative to virtualize the at least one NVMe SSD.

10. A method, comprising:
receiving a transmission at a Peripheral Component Interconnect Express (PCIe) switch with Erasure Coding logic;
processing the transmission using a snooping logic in the Erasure Coding logic; and
delivering the transmission to its destination by the PCIe switch.

11. The method according to claim 10 , wherein the Erasure Coding logic is drawn from a set including a Look-Aside Erasure Coding logic and a Look-Through Erasure Coding logic.

12. The method according to claim 10 , wherein processing the transmission using a snooping logic in the Erasure Coding logic includes processing the transmission using the snooping logic based at least in part on the Erasure Coding logic being active.

13. The method according to claim 10 , wherein:
receiving a transmission at a Peripheral Component Interconnect Express (PCIe) switch with Erasure Coding logic includes receiving a read request from a host;
processing the transmission using a snooping logic in the Erasure Coding logic includes replacing a host Logical Block Address (LBA) with a device LBA in the read request; and
delivering the transmission to its destination by the PCIe switch includes delivering the read request to a Non-Volatile Memory Express (NVMe) Solid State Drive (SSD).

14. The method according to claim 13 , wherein:
processing the transmission using a snooping logic in the Erasure Coding logic further includes accessing a data requested by the host in the read request from a cache based at least in part on the data being resident in the cache;
replacing a host Logical Block Address (LBA) with a device LBA in the read request includes replacing the host LBA with the device LBA in the read request based at least in part on the data not being resident in the cache; and
delivering the transmission to its destination by the PCIe switch includes delivering the read request to an NVMe SSD based at least in part on the data not being resident in the cache.

15. The method according to claim 10 , wherein:
receiving a transmission at a Peripheral Component Interconnect Express (PCIe) switch with Erasure Coding logic includes receiving a write request from a host;
processing the transmission using a snooping logic in the Erasure Coding logic includes replacing a host LBA with a device LBA in the write request; and
delivering the transmission to its destination by the PCIe switch includes delivering the write request to an NVMe SSD.

16. The method according to claim 10 , wherein:
receiving a transmission at a Peripheral Component Interconnect Express (PCIe) switch with Erasure Coding logic includes receiving a response from an NVMe SSD;
processing the transmission using a snooping logic in the Erasure Coding logic includes replacing a device LBA in the response with a host LBA; and
delivering the transmission to its destination by the PCIe switch includes delivering the response to a host.

17. The method according to claim 10 , further comprising:
detecting that a new NVMe SSD is connected to the PCIe switch; and
adding the new NVMe SSD to the capacity of a virtual storage device.

18. The method according to claim 10 , further comprising:
detecting a failed NVMe SSD connected to the PCIe switch; and
performing Erasure Coding recovery of data stored on the failed NVMe SSD.

19. An article, comprising a non-transitory storage medium, the non-transitory storage medium having stored thereon instructions that, when executed by a machine, result in:
receiving a transmission at a Peripheral Component Interconnect Express (PCIe) switch with Erasure Coding logic;
processing the transmission using a snooping logic in the Erasure Coding logic; and
delivering the transmission to its destination by the PCIe switch.

20. The article according to claim 19 , wherein the Erasure Coding logic is drawn from a set including a Look-Aside Erasure Coding logic and a Look-Through Erasure Coding logic.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Olarig Sompong Paul
• WORLEY Fred
• Pinto Oscar P

Classifications

• G06F3/0683

  Plurality of storage devices · CPC title

• G06F13/4022

  using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title

• G06F3/061

  Improving I/O performance · CPC title

• G06F13/1668 Primary

  Details of memory controller · CPC title

• G06F2213/0026

  PCI express · CPC title