Display device

Patent metadata

Field	Value
Publication number	US-12495688-B2
Application number	US-202318526207-A
Country	US
Kind code	B2
Filing date	Dec 1, 2023
Priority date	Feb 25, 2020
Publication date	Dec 9, 2025
Grant date	Dec 9, 2025

Abstract

A display device includes a first semiconductor layer disposed on a substrate; a first insulating layer disposed on the first semiconductor layer; a scan line disposed on the first insulating layer; a second insulating layer on the scan line; an inverted scan line on the second insulating layer; a third insulating layer disposed on the inverted scan line; a second semiconductor layer disposed on the third insulating layer; a fourth insulating layer disposed on the second semiconductor layer; an initializing voltage line disposed on the fourth insulating layer and overlapping the scan line; a first transistor including a channel disposed in the first semiconductor layer and receiving a gate signal through the scan line; and a second transistor including a channel disposed in the second semiconductor layer and receiving a gate signal through the inverted scan line.

First claim

What is claimed is:

1 . A display device comprising:
a first transistor including a first semiconductor layer; a second transistor including a second semiconductor layer and electrically connected to the first transistor; a first insulating layer disposed on the first semiconductor layer and the second semiconductor layer; a first gate line disposed on the first insulating layer; a second insulating layer disposed on the first gate line; a second gate line disposed on the second insulating layer; a third insulating layer disposed on the second gate line; a third transistor including a third semiconductor layer disposed on the third insulating layer and electrically connected to the first transistor; a fourth insulating layer disposed on the third semiconductor layer; an initializing voltage line carrying an initializing control signal disposed on the fourth insulating layer; a fifth insulating layer disposed on the initializing voltage line; a data line carrying a data signal disposed on the fifth insulating layer; a driving voltage line carrying a driving voltage disposed on the fifth insulating layer; a shielding electrode electrically connected to the initializing voltage line and overlapping at least a portion of a channel of the third semiconductor layer, the shielding electrode and at least one of the data line and the driving voltage line being disposed on a same layer; and a light emitting diode electrically connected to the first transistor.

2 . The display device of claim 1 , wherein
the first gate line extends in a first direction, and the initializing voltage line extends in the first direction and overlaps the first gate line.

3 . The display device of claim 1 , wherein
the first gate line is electrically connected to a gate electrode of the second transistor, and the second gate line is electrically connected to a gate electrode of the third transistor.

4 . The display device of claim 1 , wherein the shielding electrode overlaps a gate electrode of the third transistor.

5 . The display device of claim 1 , wherein
the initializing voltage line extends in a first direction, and the shielding electrode extends in a second direction intersecting the first direction.

6 . The display device of claim 5 , further comprising:
a first connecting member disposed on the fifth insulating layer and electrically connecting a gate electrode of the third transistor and the third semiconductor layer, wherein the data line extends in the second direction, and the shielding electrode is disposed between the first connecting member and the data line in the first direction.

7 . The display device of claim 6 , wherein the first connecting member does not overlap the second gate line.

8 . The display device of claim 6 , further comprising:
a seventh transistor including a seventh semiconductor layer and electrically connected to the light emitting diode, and a second connecting member disposed on the fifth insulating layer and electrically connecting the seventh semiconductor layer and the initializing voltage line, wherein the shielding electrode extends from the second connecting member.

9 . The display device of claim 8 , wherein the shielding electrode is integral with the second connecting member.

10 . The display device of claim 1 , further comprising:
a fourth transistor including a fourth semiconductor layer disposed on the third insulating layer and electrically connected to the first transistor and the third transistor, and a third gate line disposed on the fourth insulating layer and electrically connected to a gate electrode of the fourth transistor, wherein the shielding electrode extends across the third gate line.

11 . The display device of claim 1 , wherein the third transistor includes:
a lower gate electrode disposed between the second insulating layer and the third insulating layer; and an upper gate electrode disposed between the fourth insulating layer and the fifth insulating layer.

12 . The display device of claim 11 , wherein the upper gate electrode is electrically connected to the lower gate electrode through an opening of the third insulating layer and the fourth insulating layer.

13 . The display device of claim 1 , further comprising:
a sixth insulating layer disposed on the data line, and a data connecting line disposed on the sixth insulating layer and electrically connected to the data line through an opening of the sixth insulating layer.

14 . The display device of claim 13 , wherein the shielding electrode and at least one of the data line and the driving voltage line are disposed between the fifth insulating layer and the sixth insulating layer.

15 . The display device of claim 1 , further comprising:
a second shielding electrode disposed between the fourth insulating layer and the fifth insulating layer and electrically connected to the driving voltage line.

Assignees

• Samsung Display Co Ltd

Inventors

• Son Se Wan
• Ko Moo Soon
• Baek Kyung Hyun
• Seong Seok Je
• Lee Jae Hyun
• Lee Jeong-Soo
• Lee Ji Seon
• Cho Yoon-Jong

Classifications

• H10K59/126

  Shielding, e.g. light-blocking means over the TFTs · CPC title

• H10K59/124

  Insulating layers formed between TFT elements and OLED elements · CPC title

• G09G3/32

  semiconductive, e.g. using light-emitting diodes [LED] · CPC title

• G09G2300/0809

  Several active elements per pixel in active matrix panels · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title