Thin film transistor display panel and method for manufacturing the same

US9601518B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9601518-B2
Application numberUS-201514856405-A
CountryUS
Kind codeB2
Filing dateSep 16, 2015
Priority dateApr 8, 2015
Publication dateMar 21, 2017
Grant dateMar 21, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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Abstract

Official abstract text for this publication.

A thin film transistor display panel including: a first insulating substrate; a first semiconductor disposed between the first insulating substrate and a first gate insulating layer; a gate electrode disposed on the first gate insulating layer, the gate electrode overlapping the first semiconductor; a second gate insulating layer disposed on the gate electrode; a second semiconductor disposed on the second gate insulating layer, the second semiconductor overlapping the gate electrode; an interlayer insulating layer disposed on the second semiconductor; and a source electrode and a drain electrode disposed on the interlayer insulating layer spaced apart from each other, the source electrode and the drain electrode connected to the first semiconductor and the second semiconductor.

First claim

Opening claim text (preview).

What is claimed is: 1. A thin film transistor display panel comprising: a first insulating substrate; a first semiconductor disposed between the first insulating substrate and a first gate insulating layer; a gate electrode disposed on the first gate insulating layer, the gate electrode overlapping the first semiconductor; a second gate insulating layer disposed on the gate electrode; a second semiconductor disposed on the second gate insulating layer, the second semiconductor overlapping the gate electrode; an interlayer insulating layer disposed on the second semiconductor; and a source electrode and a drain electrode disposed on the interlayer insulating layer spaced apart from each other, the source electrode and the drain electrode connected to the first semiconductor and the second semiconductor. 2. The thin film transistor display panel of claim 1 , wherein: each of the first gate insulating layer, the second gate insulating layer, the second semiconductor, and the interlayer insulating layer comprises a first contact hole and a second contact hole. 3. The thin film transistor display panel of claim 2 , wherein: the source electrode is electrically connected to the first semiconductor and the second semiconductor through the first contact hole, the drain electrode is electrically connected to the first semiconductor and the second semiconductor through the second contact hole. 4. The thin film transistor display panel of claim 1 , wherein: each of the first semiconductor and the second semiconductor comprises oxide semiconductors. 5. The thin film transistor display panel of claim 1 , wherein: two channel regions are respectively formed in the first semiconductor and the second semiconductor in response to a gate signal applied to the gate electrode. 6. The thin film transistor display panel of claim 1 , further comprising: an upper gate electrode disposed on the interlayer insulating layer. 7. The thin film transistor display panel of claim 6 , wherein: the upper gate electrode is made of a same material as the source electrode and the drain electrode, and disposed in a same layer as the source electrode and the drain electrode. 8. The thin film transistor display panel of claim 6 , wherein: three channel regions are respectively formed in the first semiconductor and the second semiconductor by a gate signal applied to the gate electrode and the upper gate electrode. 9. The thin film transistor display panel of claim 6 , wherein: each of the second gate insulating layer and the interlayer insulating layer comprises a third contact hole. 10. The thin film transistor display panel of claim 9 , wherein: the gate electrode and the upper gate electrode are electrically connected through the third contact hole.

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What does patent US9601518B2 cover?
A thin film transistor display panel including: a first insulating substrate; a first semiconductor disposed between the first insulating substrate and a first gate insulating layer; a gate electrode disposed on the first gate insulating layer, the gate electrode overlapping the first semiconductor; a second gate insulating layer disposed on the gate electrode; a second semiconductor disposed o…
Who is the assignee on this patent?
Samsung Display Co Ltd
What technology area does this patent fall under?
Primary CPC classification H01L27/1225. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Mar 21 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).