Semiconductor device including air gap

Patent metadata

Field	Value
Publication number	US-12495573-B2
Application number	US-202217717268-A
Country	US
Kind code	B2
Filing date	Apr 11, 2022
Priority date	Oct 15, 2021
Publication date	Dec 9, 2025
Grant date	Dec 9, 2025

Abstract

A semiconductor device of the disclosure includes an active pattern extending on a substrate in a first direction, a gate structure extending on the active pattern in a second direction intersecting the first direction, a source/drain region disposed on at least one side of the gate structure, a source/drain contact connected to the source/drain region, and a contact insulating layer disposed on the source/drain contact. The contact insulating layer includes at least one air gap. The air gap is disposed on an upper surface of the source/drain contact.

First claim

What is claimed is:

1 . A semiconductor device comprising:
an active pattern extending on a substrate in a first direction; a gate structure extending on the active pattern in a second direction intersecting the first direction; a source/drain region disposed on at least one side of the gate structure; a source/drain contact connected to the source/drain region; and a contact insulating layer disposed on the source/drain contact, the contact insulating layer comprising at least one air gap, wherein the air gap is disposed on an upper surface of the source/drain contact to overlap with the upper surface of the source/drain contact in a direction perpendicular to the substrate.

2 . The semiconductor device according to claim 1 , wherein the contact insulating layer is spaced apart from the source/drain region.

3 . The semiconductor device according to claim 1 , wherein the contact insulating layer comprises silicon oxycarbonitride (SiOC).

4 . The semiconductor device according to claim 1 , wherein the source/drain contact comprises:
a lower contact disposed on the source/drain region; and an upper contact upwardly protruding from the lower contact.

5 . The semiconductor device according to claim 4 , wherein:
the air gap is disposed on the lower contact; and the air gap is disposed on one side of the upper contact.

6 . The semiconductor device according to claim 1 , wherein the contact insulating layer comprises:
a base layer comprising the air gap; and a protrusion protruding from a bottom surface of the base layer toward the substrate.

7 . The semiconductor device according to claim 6 , wherein the protrusion includes a width in the first direction, and wherein the width in the first direction gradually decreases as the protrusion extends away from the base layer.

8 . The semiconductor device according to claim 1 , wherein the upper surface of the source/drain contact is convex toward the contact insulating layer.

9 . The semiconductor device according to claim 1 , wherein:
the source/drain contact comprises
a source/drain contact plug, and
a source/drain contact harrier layer covering a side surface and a bottom surface of the source/drain contact plug; and
an upper end of the source/drain contact plug is disposed at a higher level than an upper end of the source/drain contact barrier layer.

10 . The semiconductor device according to claim 1 , wherein:
the gate structure comprises
a gate electrode,
a gate insulating layer surrounding a sidewall and a bottom surface of the gate electrode, and
a gate capping layer disposed on the gate electrode and the gate insulating layer; and
a lower end of the air gap is disposed at a higher level than a lower end of the gate capping layer.

11 . The semiconductor device according to claim 1 , wherein an upper perimeter of the air gap is disposed at a same level as an upper surface of the contact insulating layer.

12 . The semiconductor device according to claim 1 , further comprising:
an upper interlayer insulating layer disposed on the gate structure and the contact insulating layer, wherein an upper end of the air gap is immediately adjacent to the upper interlayer insulating layer.

13 . The semiconductor device according to claim 12 , wherein the upper interlayer insulating layer comprises an extension extending into the contact insulating layer.

14 . The semiconductor device according to claim 1 , further comprising:
an interlayer insulating layer contacting the source/drain region and the source/drain contact, wherein the contact insulating layer contacts the interlayer insulating layer.

15 . The semiconductor device according to claim 1 , further comprising:
channel patterns disposed on the active pattern and vertically spaced apart from one another, wherein the gate structure comprises a gate insulating layer and a gate electrode surrounding the channel patterns.

16 . A semiconductor device comprising:
an active pattern extending on a substrate in a first direction; an element isolation layer covering a lower portion of the active pattern; a gate structure extending on the active pattern and the element isolation layer in a second direction intersecting the first direction; source/drain regions disposed on opposite sides of the gate structure; a first source/drain contact connected to the source/drain regions on a first side of the gate structure; air interlayer insulating layer contacting the source/drain regions and the first source/drain contact; and a contact insulating layer disposed on the first source/drain contact, the contact insulating layer comprising at least one air gap, wherein the air gap is disposed on an upper surface of the first source/drain contact to overlap with the upper surface of the first source/drain contact in a direction perpendicular to the substrate.

17 . The semiconductor device according to claim 16 , further comprising:
a second source/drain contact connected to the source/drain regions on a second side of the gate structure, wherein the second source/drain contact has a height different from a height of the first source/drain contact.

18 . The semiconductor device according to claim 17 , wherein an upper surface of the contact insulating layer is coplanar with an upper surface of the second source/drain contact.

19 . The semiconductor device according to claim 16 , wherein:
the first source/drain contact comprises
a lower contact on the source/drain region, and
an upper contact upwardly protruding from the lower contact; and
the air gap is disposed on each of opposite sides of the upper contact.

20 . A semiconductor device comprising:
an active pattern extending on a substrate in a first direction; an element isolation layer covering a lower portion of the active pattern; a gate structure intersecting the first direction on the active pattern and the element isolation layer; a gate contact connected to the gate structure; a source/drain region disposed on at least one side of the gate structure; a source/drain contact connected to the source/drain region on one side of the gate structure; an interlayer insulating layer contacting the source/drain region and the source/drain contact; a contact insulating layer disposed on the source/drain contact, the contact insulating layer comprising at least one air gap; a first wiring structure connected to the source/drain contact; and a second wiring structure connected to the gate contact, wherein the air gap is disposed on an upper surface of the source/drain contact to overlap with the upper surface of the source/drain contact in a direction perpendicular to the substrate.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Hong Sooyeon
• Bae Deokhan
• Park Juhun
• Lee Yuri
• Jung Yoonyoung

Classifications

• H10W20/47

  comprising two or more dielectric layers having different properties, e.g. different dielectric constants · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/495

  Capacitive arrangements or effects of, or between wiring layers · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title