Capacitor with dual dielectric layers

Patent metadata

Field	Value
Publication number	US-12495559-B2
Application number	US-202117483795-A
Country	US
Kind code	B2
Filing date	Sep 23, 2021
Priority date	Sep 23, 2021
Publication date	Dec 9, 2025
Grant date	Dec 9, 2025

Abstract

Embodiments described herein may be related to apparatuses, processes, and techniques related to increasing the capacitance density of MIM capacitors on dies or within packages. In particular, a MIM stack is disclosed that has multiple insulator layers between the metal, in order to increase the dielectric constant of the MIM stack. In particular, the first dielectric layer may include strontium, titanium, and oxygen and may be physically coupled with a second dielectric layer that may include barium, strontium, titanium, and oxygen. Other embodiments may be described and/or claimed.

First claim

What is claimed is:

1 . A capacitor comprising:
a first metal layer; a first dielectric layer on the first metal layer, the first dielectric layer comprising strontium, titanium, and oxygen; a second dielectric layer on the first dielectric layer, the second dielectric layer comprising barium, strontium, titanium, and oxygen; and a third dielectric layer on the second dielectric layer, the third dielectric layer comprising hafnium and oxygen.

2 . The capacitor claim 1 , further comprising a second metal layer over the third dielectric layer.

3 . The capacitor of claim 2 , wherein the second metal layer includes ruthenium.

4 . The capacitor of claim 1 , wherein the first metal layer includes ruthenium or iridium.

5 . The capacitor of claim 1 , wherein a thickness of the first metal layer ranges from 1 nm to 100 nm.

6 . The capacitor of claim 1 , wherein a thickness of the third dielectric layer ranges from 0.2 nm to 5 nm.

7 . The capacitor of claim 1 , further comprising:
another layer beneath and coupled with the first metal layer, wherein the other layer includes tantalum or titanium.

8 . The capacitor of claim 7 , wherein a thickness of the other layer ranges from 0.5 nm to 20 nm.

9 . The capacitor of claim 7 , wherein the other layer is coupled with a substrate.

10 . A package comprising:
a substrate; and a capacitor coupled with the substrate, the capacitor comprising:
a first metal layer that includes ruthenium or iridium;
a first dielectric layer on the first metal layer, the first dielectric layer comprising strontium, titanium, and oxygen;
a second dielectric layer on the first dielectric layer, the second dielectric layer comprising barium, strontium, titanium, and oxygen;
a third dielectric layer on the second dielectric layer, the third dielectric layer comprising hafnium and oxygen; and
a second metal layer that includes ruthenium, the second metal layer over the third dielectric layer.

11 . The package of claim 10 , wherein the first metal layer has a first side and a second side opposite the first side, wherein the second side of the first metal layer is coupled with the first dielectric layer, and wherein the substrate is coupled with the first side of the first metal layer.

12 . The package of claim 11 , further comprising another layer between the first metal layer and the substrate, the other layer having a first side and a second side opposite the first side, wherein the first side of the other layer is coupled with the substrate and wherein the second side of the other layer is coupled with the first side of the first dielectric layer.

13 . The package of claim 12 , wherein the other layer includes tantalum or titanium and has a thickness between the first side and the second side that ranges from 0.5 nm to 20 nm.

14 . The package of claim 10 , wherein the capacitor has a K value of greater than 160.

Assignees

• Intel Corp

Inventors

• Oguz Kaan
• Tung I-Cheng
• Lin Chia-Ching
• Chang Sou-Chi
• Metz Matthew V
• Avci Uygar E
• Sen Gupta Arnab

Classifications

• H10D1/694 Primary

  comprising noble metals or noble metal oxides · CPC title