Liquid metal interconnect for modular system on an interposer server architecture

Patent metadata

Field	Value
Publication number	US-12494435-B2
Application number	US-202117559431-A
Country	US
Kind code	B2
Filing date	Dec 22, 2021
Priority date	Dec 22, 2021
Publication date	Dec 9, 2025
Grant date	Dec 9, 2025

Abstract

An electronic system and associated methods are disclosed. In one example, the electronic system includes an interposer including electrically conductive interposer interconnect, a first interposer surface, and a second interposer surface; a processor package including at least one processor integrated circuit (IC), the processor package attached to the first interposer surface and electrically connected to the interposer interconnect; a first liquid metal well array including multiple liquid metal wells attached to a second interposer surface and the interposer interconnect; a second liquid metal well array including a first array surface attached to the first interposer surface and the interposer interconnect; and a packaged companion IC to the processor IC attached to a second array surface of the second liquid metal well array.

First claim

The invention claimed is:

1 . An electronic system, comprising:
a first interposer comprising an electrically conductive first interposer interconnect; a processor package comprising at least one processor integrated circuit (IC), the processor package attached to a first surface of the first interposer and connected to the first interposer interconnect; a first liquid metal well array comprising multiple liquid metal wells attached to a second surface of the first interposer and connected to the first interposer interconnect; a second interposer comprising an electrically conductive second interposer interconnect; an IC package attached to a first surface of the second interposer and connected to the second interposer interconnect; and a second liquid metal well array comprising multiple liquid metal wells attached to a second surface of the second interposer and connected to the second interposer interconnect, wherein the first liquid metal well array is attached to the second surface of the second interposer and connected to the second interposer interconnect, and the second liquid metal well array is attached to the second surface of the first interposer and connected to the first interposer interconnect.

2 . The electronic system of claim 1 , wherein the first and second interposers are first and second mother boards.

3 . The electronic system of claim 1 , comprising a companion component to the processor IC attached to the first surface of the first interposer and connected to the first interposer interconnect.

4 . The electronic system of claim 3 , wherein the companion component comprises one of a memory IC, a field programmable gate array (FPGA), a voltage regulator IC, at least one circuit component of a voltage regulator circuit, or a circuit package that includes a high-speed input-output (HSIO) connector.

5 . The electronic system of claim 1 , wherein the multiple liquid metal wells of the first and second liquid metal well arrays are two-sided liquid metal wells.

6 . The electronic system of claim 1 , wherein the multiple liquid metal wells of the first and second liquid metal well arrays are one-sided liquid metal wells.

7 . The electronic system of claim 6 , wherein a first surface of the first liquid metal well array is attached to the second surface of the first interposer using solder bumps and the multiple liquid metal wells of the first liquid metal well array are attached to conductive pillars of the second surface of the second interposer.

8 . The electronic system of claim 7 , wherein a first surface of the second liquid metal well array is attached to the second surface of the first interposer using solder bumps and the multiple liquid metal wells of the second liquid metal well array are attached to conductive pillars of the second surface of the first interposer.

9 . The electronic system of claim 1 , wherein the IC package of the second interposer is a second processor package comprising a second processor IC.

10 . The electronic system of claim 9 , wherein the second interposer comprises a companion component to the second processor IC attached to the first surface of the second interposer and connected to the second interposer interconnect.

11 . The electronic system of claim 10 , wherein the companion component comprises system memory.

12 . An apparatus, comprising:
a first interposer comprising a first interposer interconnect; a processor package attached to a first surface of the first interposer and connected to the first interposer interconnect; a first liquid metal well array attached to a second surface of the first interposer and connected to the first interposer interconnect; a second interposer comprising a second interposer interconnect; an integrated circuit (IC) package attached to a first surface of the second interposer and connected to the second interposer interconnect; and a second liquid metal well array attached to a second surface of the second interposer and connected to the second interposer interconnect, wherein the first liquid metal well array is attached to the second surface of the second interposer and connected to the second interposer interconnect, and the second liquid metal well array is attached to the second surface of the first interposer and connected to the first interposer interconnect.

13 . The apparatus of claim 12 , wherein the first and second interposers are first and second mother boards.

14 . The apparatus of claim 12 , comprising a companion component to the processor package attached to the first surface of the first interposer and connected to the first interposer interconnect.

15 . The apparatus of claim 14 , wherein the companion component comprises one of a memory IC, a field programmable gate array (FPGA), a voltage regulator IC, at least one circuit component of a voltage regulator circuit, or a circuit package that includes a high-speed input-output (HSIO) connector.

16 . The apparatus of claim 12 , wherein the first and second liquid metal well arrays comprise multiple two-sided liquid metal wells.

17 . The apparatus of claim 12 , wherein the first and second liquid metal well arrays comprise multiple one-sided liquid metal wells.

18 . The apparatus of claim 17 , wherein a first surface of the first liquid metal well array is attached to the second surface of the first interposer using solder bumps and the multiple one-sided liquid metal wells of the first liquid metal well array are attached to conductive pillars of the second surface of the second interposer.

19 . The apparatus of claim 18 , wherein a first surface of the second liquid metal well array is attached to the second surface of the first interposer using solder bumps and the multiple one-sided liquid metal wells of the second liquid metal well array are attached to conductive pillars of the second surface of the first interposer.

20 . The apparatus of claim 12 , wherein the IC package of the second interposer is a second processor package.

21 . The apparatus of claim 20 , wherein the second interposer comprises a companion component to the second processor package attached to the first surface of the second interposer and connected to the second interposer interconnect.

22 . The apparatus of claim 21 , wherein the companion component comprises system memory.

Assignees

• Intel Corp

Inventors

• Meyyappan Karumbu
• Smalley Jeffory L
• Murtagian Gregorio
• Nekkanty Srikant
• Tadayon Pooya
• Moret Eric J M
• Sahu Bijoyraj

Classifications

• H10W90/401

  characterised by multiple insulating or insulated package substrates, interposers or RDLs · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W70/635

  Through-vias · CPC title

• H10W70/611 Primary

  for connecting multiple chips together · CPC title

• H10W40/22

  characterised by their shape, e.g. having conical or cylindrical projections · CPC title