Amplifier modules with power transistor die and peripheral ground connections

Patent metadata

Field	Value
Publication number	US-12494380-B2
Application number	US-202418637489-A
Country	US
Kind code	B2
Filing date	Apr 17, 2024
Priority date	Apr 17, 2020
Publication date	Dec 9, 2025
Grant date	Dec 9, 2025

Abstract

A power amplifier module includes a module substrate, a power transistor die, and a heat spreader. The module substrate has first, second, and third module pads exposed at a mounting surface. The power transistor die has an input/output surface that faces the mounting surface, an opposed ground surface, an input pad electrically coupled to the first module pad, an output pad electrically coupled to the second module pad, and an integrated power transistor. In an embodiment, the power transistor is a field effect transistor with a gate terminal coupled to the input pad, a drain terminal coupled to the output pad, and a source terminal coupled to the ground surface. The heat spreader has a thermal contact surface that is physically and electrically coupled to the ground surface of the power transistor die. An electrical ground contact structure is connected between the thermal contact surface and the third module pad.

First claim

What is claimed is:

1 . A method of fabricating a power amplifier module, the method comprising:
coupling a first power transistor die to a module substrate,
wherein the module substrate has a mounting surface, a first module pad exposed at the mounting surface, a second module pad exposed at the mounting surface, and a third module pad exposed at the mounting surface,
wherein the first power transistor die has with an input/output (I/O) surface, a ground surface opposite the I/O surface, an input pad exposed at the I/O surface, an output pad exposed at the I/O surface, an integrated power transistor with a control terminal electrically coupled to the input pad, a first current-carrying terminal electrically coupled to the output pad, and a second current-carrying terminal electrically coupled to the ground surface, and
wherein the first power transistor die is coupled to the module substrate with the I/O surface facing the mounting surface, the input pad electrically coupled to the first module pad, and the output pad electrically coupled to the second module pad;
physically and electrically coupling the ground surface of the first power transistor die to a first heat spreader with a first thermal contact surface, a second thermal contact surface, sidewalls extending between the first and second thermal contact surfaces, and a patterned mask layer on the first thermal contact surface
wherein the first thermal contact surface includes an interior area and a peripheral area that extends parallel to the interior area between the interior area and a first sidewall of the sidewalls,
wherein the patterned mask layer on the first thermal contact surface includes an interior opening that exposes the interior area of the first thermal contact surface, and a peripheral opening that exposes the peripheral area of the first thermal contact surface, and
wherein the interior area is physically and electrically coupled through the interior opening to the ground surface of the first power transistor die; and
connecting an electrical ground contact structure through the peripheral opening to the peripheral area of the first thermal contact surface; and connecting the electrical ground contact structure to the third module pad of the module substrate.

2 . The method of claim 1 , further comprising:
electrically coupling an input signal contact of the module substrate to the first module pad; electrically coupling an output signal contact of the module substrate to the second module pad; and electrically coupling a system ground contact of the module substrate to the third module pad.

3 . The method of claim 1 , further comprising:
connecting an input contact structure between the input pad of the first power transistor die and the first module pad; and connecting an output contact structure between the output pad of the first power transistor die and the second module pad.

4 . The method of claim 3 , wherein the input contact structure and the output contact structure each include one or more components selected from a conductive pillar and solder.

5 . The method of claim 1 , wherein the electrical ground contact structure comprises one or more components selected from a conductive pillar and solder.

6 . The method of claim 1 , wherein the first heat spreader comprises a thermally-and electrically-conductive material selected from copper or another bulk conductive material.

7 . The method of claim 1 , wherein the integrated power transistor is a field effect transistor, the control terminal is a gate terminal of the field effect transistor, the first current-carrying terminal is a drain terminal of the field effect transistor, and the second current-carrying terminal is a source terminal of the field effect transistor.

8 . The method of claim 1 , wherein the first power transistor die comprises:
a semiconductor substrate with a first surface and a second surface opposite the first surface, wherein the second surface of the semiconductor substrate corresponds to the ground surface of the first power transistor die; and a build-up structure formed on the first surface of the semiconductor substrate, wherein an exposed surface of the build-up structure corresponds to the I/O surface of the first power transistor die.

9 . The method of claim 8 , wherein the first power transistor die further comprises:
a conductive layer on the second surface of the semiconductor substrate; and a plurality of through substrate vias, wherein each of the through substrate vias extend from the first surface of the semiconductor substrate to the second surface of the semiconductor substrate, and wherein the second current-carrying terminal of the integrated power transistor is electrically coupled to the conductive layer through the plurality of through substrate vias.

10 . The method of claim 1 , further comprising:
covering the mounting surface of the module substrate, the first power transistor die, and sidewalls of the first heat spreader with encapsulant material.

11 . The method of claim 10 , wherein:
a surface of the encapsulant material is co-planar with the second thermal contact surface.

12 . The method of claim 11 , further comprising:
coupling a heat dissipation structure to the second thermal contact surface.

13 . The method of claim 1 , further comprising:
coupling a second power transistor die to the mounting surface; and physically and electrically coupling a second heat spreader to the second power transistor die, wherein the first power transistor die corresponds to a main amplifier of a Doherty power amplifier, and the second power transistor die corresponds to a peaking amplifier of the Doherty power amplifier.

14 . The method of claim 1 , wherein coupling the first power transistor die to the module substrate comprises:
coupling an input contact structure to the input pad; coupling an output contact structure to the output pad; aligning the input and output contact structures with the first and second module pads; and reflowing solder to connect the input contact structure to the first module pad, and to connect the output contact structure to the second module pad.

15 . The method of claim 3 , wherein each of the input and output contact structures includes a rigid conductive pillar.

16 . The method of claim 1 , wherein the electrical ground contact structure comprises solder.

17 . The method of claim 1 , wherein the electrical ground contact structure comprises a rigid conductive pillar.

Assignees

• Nxp Usa Inc

Inventors

• Maalouf Elie A
• Pabst Eduard Jan

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/073

  of die-attach connectors · CPC title

• H10W72/877

  Bump connectors and die-attach connectors · CPC title

• H10W72/9445

  Top-view layouts, e.g. mirror arrays · CPC title

• H10W72/932

  Plan-view shape, i.e. in top view · CPC title