Multi-mode memory subsystem including control and data modules for buffering and testing

Patent metadata

Field	Value
Publication number	US-12494262-B2
Application number	US-202418402549-A
Country	US
Kind code	B2
Filing date	Jan 2, 2024
Priority date	Apr 14, 2008
Publication date	Dec 9, 2025
Grant date	Dec 9, 2025

Abstract

A memory module comprises memory devices, a data module and a control module. The memory module is operable in a first mode in which at least some of the memory devices are accessed by a system memory controller in a computer system for memory read and/or write operations at a memory access speed, the control module is configured to register address and control signals associated with the memory read and/or write operations, and the data module is configured to propagate data signals between the at least some of the memory devices and the memory controller. The memory module is further operable in a second mode in which the memory devices are not accessed by the system memory controller for memory read or write operations, and the data module is configured to communicate data signals with at least some of the memory devices at the memory access speed.

First claim

We claim:

1 . A memory subsystem operable in a computer system, the computer system including a memory controller configurable to communicate with the memory subsystem via a set of system signal lines including system control/address (C/A) signal lines and system data signal lines, the memory subsystem comprising:
memory devices having C/A ports and data ports and configurable to receive input C/A signals via the C/A ports and to receive/output data signals via the data ports in response to the input C/A signals; a control module coupled to the C/A ports of the memory devices via subsystem C/A signal lines; and a data module coupled to the data ports of the memory devices via subsystem data signal lines; wherein the memory subsystem is operable in a normal mode and a test mode; wherein, during the normal mode: the control module is configured to receive system C/A signals from the memory controller via the system C/A signal lines, and to transmit subsystem C/A signals to at least some of the memory devices based on the system C/A signals; and the data module is configured to propagate data signals between the subsystem data signal lines and the system data signal lines, the data signals being received or output by at least some of the memory devices in response to the subsystem C/A signals; wherein, during the test mode: the control module is configured to transmit test C/A signals to at least some of the memory devices; the data module is configured to isolate data paths from the system data signal lines to the subsystem data signal lines; and the data module is further configured to generate test data signals and to transmit the test data signals to at least some of the memory devices via at least some of the subsystem data signal lines, the test signals being received by and written into memory locations in at least some of the memory devices in response to the test C/A signals.

2 . The memory subsystem of claim 1 , wherein the data module includes data generation circuitry configured to generate the test data signals and data path control circuitry configured to selectively output data from the system memory controller or data from the data generation elements to the memory devices via the subsystem data signal lines.

3 . The memory subsystem of claim 2 , wherein the data module includes first data paths from the system data signal lines to the subsystem data signal lines, and wherein the first data paths are disabled during the test mode.

4 . The memory subsystem of claim 3 , wherein the data module further includes second data paths from the subsystem data signal lines to the system data signal lines, and wherein the second data paths are disabled during the test mode.

5 . The memory subsystem of claim 2 , wherein the data generation circuitry includes a linear feedback shift register (LFSR) configured to generate random or pseudorandom test data.

6 . The memory subsystem of claim 2 , wherein the test data signals have data patterns that are programmable by the data module based on information received by the data module.

7 . The memory subsystem of claim 6 , wherein the information is received by the control module from the system memory controller and provided to the data module.

8 . The memory subsystem of claim 2 , wherein the system data signal lines include a plurality of groups of data signal lines, wherein the memory devices include a plurality of groups of memory devices coupled to respective groups of memory subsystem data signal lines, each group of the plurality of groups of memory devices corresponding to a respective group of the plurality of groups of data signal lines, and wherein the data module includes a plurality of data handlers corresponding, respectively, to the plurality of groups of memory devices, each data handler including respective data generation circuitry configured to generate test data signals for outputting to a corresponding group of memory devices via a corresponding group of memory subsystem data signal lines, the each data handler further including respective data paths between the corresponding group of memory devices and a corresponding group of data signal lines.

9 . A memory subsystem operable in a computer system, the computer system including a memory controller configurable to communicate with the memory subsystem via a set of system signal lines including system control/address (C/A) signal lines and system data signal lines, the memory subsystem comprising:
memory devices having C/A ports and data ports and configured to receive C/A signals via the C/A ports and receive/output data signals via the data ports; a control module coupled to the C/A ports of the memory devices via subsystem C/A signal lines; and a data module coupled to the data ports of the memory devices via subsystem data signal lines; wherein the memory subsystem is operable in a normal mode and a test mode; wherein, during the normal mode: the control module is configured to receive system C/A signals from the memory controller via the system C/A signal lines, and to transmit subsystem C/A signals to at least some of the memory devices based on the system C/A signals; and the data module is configured to propagate data signals between the subsystem data signal lines and the system data signal lines, the data signals being received or output by at least some of the memory devices in response to the subsystem C/A signals; wherein, during the test mode: the control module is configured to transmit test C/A signals to at least some of the memory devices; the data module is configured to isolate data paths from the system data signal lines to the subsystem data signal lines; and the data module is further configured to receive test data signals from at least some of the memory devices via at least some of the subsystem data signal lines, to compare data patterns in the test data signals with expected data patterns, and to output signals indicating whether the data patterns in the test data signals match the expected data patterns, the test data signals being output by at least some of the memory devices in response to the test C/A signals received via the subsystem C/A signal lines.

10 . The memory subsystem of claim 9 , wherein the data module includes data verification circuitry configured to verify whether the data patterns match the expected data patterns, and data path control circuitry configured to selectively direct signals received via the subsystem data signal lines to the system data signal lines or to the data verification circuitry depending on whether the memory subsystem is in the normal mode or the test mode.

11 . The memory subsystem of claim 10 , wherein the verification circuitry includes memory that stores the expected data patterns.

12 . The memory subsystem of claim 10 , wherein the verification circuitry is configured to calculate the expected data patterns.

13 . The memory subsystem of claim 10 , wherein the data module includes first data paths from the subsystem data signal lines to the system data signal lines, and wherein the first data paths are disabled during the test mode.

14 . The memory subsystem of claim 13 , wherein the data module further includes second data paths from the system data signal lines to the subsystem data signal lines, and wherein the second data paths are disabled during the test mode.

15 . The memory subsystem of claim 10 , wherein the system data signal lines include a plurality of groups of data signal lines, wherein the memory devices include a plurality of groups of memory devices coupled to respectiv

Assignees

• Netlist Inc

Inventors

• Lee Hyun
• Bhakta Jayesh R
• Choi Soonju

Classifications

• G11C29/12 Primary

  Built-in arrangements for testing, e.g. built-in self testing [BIST] {or interconnection details} · CPC title

• G11C5/04

  Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports · CPC title

• G11C29/10 Primary

  Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns · CPC title