Semiconductor memory systems with on-die data buffering

Patent metadata

Field	Value
Publication number	US-12493568-B2
Application number	US-202418629167-A
Country	US
Kind code	B2
Filing date	Apr 8, 2024
Priority date	Oct 16, 2012
Publication date	Dec 9, 2025
Grant date	Dec 9, 2025

Abstract

A semiconductor memory system includes a first semiconductor memory die and a second semiconductor memory die. The first semiconductor memory die includes a primary data interface to receive an input data stream during write operations and to deserialize the input data stream into a first plurality of data streams, and also includes a secondary data interface, coupled to the primary data interface, to transmit the first plurality of data streams. The second semiconductor memory die includes a secondary data interface, coupled to the secondary data interface of the first semiconductor memory die, to receive the first plurality of data streams.

First claim

What is claimed is:

1 . A memory device, comprising:
a package substrate; a semiconductor base die mounted on the package substrate and configured as a master die, the semiconductor base die comprising a primary interface to couple to a memory controller, the primary interface to transfer first data between the semiconductor base die and the memory controller at a first data rate, the semiconductor base die including a secondary interface; multiple memory die stacked vertically on the semiconductor base die and configured as minion die, the multiple memory die coupled to the secondary interface of the semiconductor base die by through-silicon vias, the secondary interface to transfer second data between the semiconductor base die and the multiple memory die at a second data rate, wherein the first data rate is a multiple of the second data rate; and wherein memory operations between the memory controller and any of the multiple memory die are retransmitted through the semiconductor base die.

2 . The memory device of claim 1 , wherein:
the semiconductor base die comprises a base memory die.

3 . The memory device of claim 1 , wherein:
the package substrate is configured for mounting to a module substrate.

4 . The memory device of claim 1 , wherein:
the multiple memory die comprise multiple dynamic random access memory (DRAM) die.

5 . The memory device of claim 4 , wherein:
the multiple DRAM die comprise eight DRAM die.

6 . The memory device of claim 5 , wherein:
the semiconductor base die comprises a base DRAM die.

7 . A semiconductor memory chip package, comprising:
a package substrate;
a semiconductor base IC chip mounted on the package substrate and configured as a master chip; and
multiple memory integrated circuit (IC) chips stacked vertically on the semiconductor base IC chip and configured as minion IC chips; wherein the semiconductor base IC chip further comprises
a primary interface to couple to a memory controller, the primary interface to transfer first data between the semiconductor base IC chip and the memory controller at a first data rate, and
a secondary interface to couple to the multiple memory IC chips by through-silicon vias, the secondary interface to transfer second data between the semiconductor base IC chip and the multiple memory IC chips at a second data rate, wherein the first data rate is a multiple of the second data rate;
wherein memory operations between the memory controller and any of the multiple memory IC chips are retransmitted through the semiconductor base IC chip.

8 . The semiconductor memory chip package according to claim 7 , wherein:
the semiconductor base IC chip further comprises an array of storage cells.

9 . The semiconductor memory chip package according to claim 7 , wherein:
the package substrate is configured for mounting to a module substrate.

10 . The semiconductor memory chip package according to claim 7 , wherein:
the multiple memory IC chips comprise multiple dynamic random access memory (DRAM) IC chips.

11 . The semiconductor memory chip package according to claim 10 , wherein:
the multiple DRAM IC chips comprise eight DRAM IC chips.

12 . The semiconductor memory chip package according to claim 7 , wherein:
the semiconductor base IC chip comprises a base DRAM IC chip.

13 . A semiconductor module, comprising:
a module substrate; and multiple memory devices mounted on the module substrate, wherein ones of the multiple memory devices comprise:
a package substrate disposed on the module substrate;
a semiconductor base die mounted on the package substrate and configured as a master die, the semiconductor base die comprising a primary interface to couple to a memory controller, the primary interface to transfer first data between the semiconductor base die and the memory at a first data rate, the semiconductor base die including a secondary interface;
multiple memory die stacked vertically on the semiconductor base die and configured as minion die, the multiple memory die coupled to the secondary interface of the semiconductor base die by through-silicon vias, the secondary interface to transfer second data between the semiconductor base die and the multiple memory die at a second data rate, wherein the first data rate is a multiple of the second data rate; and
wherein memory operations between the memory controller and any of the multiple memory die are retransmitted through the semiconductor base die.

14 . The semiconductor module according to claim 13 , wherein:
the semiconductor base die comprises a base memory die.

15 . The semiconductor module of claim 13 , wherein:
the multiple memory die comprise multiple dynamic random access memory (DRAM) die.

16 . The semiconductor module of claim 15 , wherein:
the multiple DRAM die comprise eight DRAM die.

17 . The semiconductor module of claim 16 , wherein:
the semiconductor base die comprises a base DRAM die.

Assignees

• Rambus Inc

Inventors

• Ware Frederick A
• Amirkhany Amir
• Rajan Suresh
• Hekmat Mohammad
• Patil Dinesh

Classifications

• G06F13/4068

  Electrical coupling · CPC title

• G11C7/1021

  Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address · CPC title

• G11C5/02

  Disposition of storage elements, e.g. in the form of a matrix array · CPC title

• G11C29/028

  with adaption or trimming of parameters · CPC title

• G11C29/023

  in clock generator or timing circuitry · CPC title