Semiconductor memory systems with on-die data buffering

Patent metadata

Field	Value
Publication number	US-10402352-B2
Application number	US-201615333001-A
Country	US
Kind code	B2
Filing date	Oct 24, 2016
Priority date	Oct 16, 2012
Publication date	Sep 3, 2019
Grant date	Sep 3, 2019

Abstract

A semiconductor memory system includes a first semiconductor memory die and a second semiconductor memory die. The first semiconductor memory die includes a primary data interface to receive an input data stream during write operations and to deserialize the input data stream into a first plurality of data streams, and also includes a secondary data interface, coupled to the primary data interface, to transmit the first plurality of data streams. The second semiconductor memory die includes a secondary data interface, coupled to the secondary data interface of the first semiconductor memory die, to receive the first plurality of data streams.

First claim

What is claimed is:

1. A DRAM integrated circuit (IC) chip comprising:
DRAM storage cells formed on the DRAM IC chip;
a primary interface formed on the DRAM IC chip for transferring data signals with a first IC chip;
a secondary interface formed on the DRAM IC chip for transferring the data signals with a second DRAM IC chip;
a command/address (C/A) interface formed on the DRAM chip for transferring C/A signals directly with the first IC chip via a C/A signal path, the C/A signal path directly coupling the first IC chip with the second DRAM IC chip;
a mode configuration interface formed on the DRAM IC chip, the mode configuration interface including a configuration register to configure use of the secondary interface;
wherein the mode configuration interface is responsive to a first mode control signal stored in the configuration register to configure the secondary interface for a first mode of operation;
wherein the mode configuration interface is responsive to a second mode control signal stored in the configuration register to configure the secondary interface for a second mode of operation that is different than the first mode of operation; and
wherein the C/A interface receives the C/A signals from the first IC chip for both the first and second modes of operation.

2. The DRAM IC chip according to claim 1 , wherein the mode configuration interface enables use of the secondary interface to retransmit write data in the first mode of operation in response to the mode control signal.

3. The DRAM IC chip according to claim 2 , further comprising:
buffer core circuitry coupled to the secondary interface, the buffer circuitry to, in the first mode of operation, retransmit the write data received by the primary interface to the second DRAM IC chip via the secondary interface.

4. The DRAM IC chip according to claim 3 , wherein the first IC chip comprises a memory controller IC chip.

5. The DRAM IC chip according to claim 1 , wherein the mode configuration interface configures use of the secondary interface to receive write data in the second mode of operation in response to the mode control signal.

6. The DRAM IC chip according to claim 3 , wherein:
the DRAM storage cells include memory core circuitry coupled to the primary interface, the memory core circuitry to transfer signals with the first IC chip via the primary interface.

7. The DRAM IC chip according to claim 6 , wherein the first IC chip is embodied as a memory controller chip.

8. A dynamic random access memory (DRAM) integrated circuit (IC) chip comprising:
DRAM storage cells formed on the DRAM IC chip;
a primary interface formed on the DRAM IC chip for transferring data signals with a logic IC chip;
a secondary interface formed on the DRAM IC chip for transferring the data signals with a second DRAM IC chip;
a command/address (C/A) interface formed on the DRAM chip for transferring C/A signals directly with the first IC chip via a C/A signal path, the C/A signal path directly coupling the first IC chip with the second DRAM IC chip;
mode configuration circuitry formed on the DRAM IC chip to configure use of the secondary interface between a first mode of operation and a second mode of operation, the mode configuration circuitry including a mode configuration interface with a configuration register; and
wherein the C/A interface receives the C/A signals from the logic IC chip for both the first and second modes of operation.

9. The DRAM IC chip according to claim 8 , wherein the mode configuration interface is responsive to a control signal to configure use of the secondary interface in a retransmit mode or a write data receive mode.

10. The DRAM IC chip according to claim 9 , further comprising:
buffer core circuitry coupled to the secondary interface, the buffer core circuitry to, in the retransmit mode, retransmit signals received by the primary interface to the second DRAM IC chip via the secondary interface.

11. The DRAM IC chip according to claim 9 , further comprising:
memory core circuitry coupled to the primary interface, the memory core circuitry to transfer signals with the logic IC chip via the primary interface when the secondary interface is configured in the retransmit mode.

12. The DRAM IC chip according to claim 11 , wherein the logic IC chip is embodied as a memory controller chip.

13. A method of operation in a dynamic random access memory (DRAM) integrated circuit (IC) chip, the method comprising:
selectively transferring data signals with a second IC chip via a primary interface formed on the DRAM IC chip;
transferring signals with a second DRAM IC chip via a secondary interface formed on the DRAM IC chip;
transferring command/address (C/A) signals directly with the second IC chip via a C/A signal path, the C/A signal path directly coupling the second IC chip with the second DRAM IC chip;
configuring use of the secondary interface between a first mode of operation and a second mode of operation with a mode configuration interface including a configuration register formed on the DRAM IC chip; and
wherein the C/A interface receives the C/A signals from the second IC chip for both the first and second modes of operation.

14. The method according to claim 13 , wherein:
the mode configuration interface is responsive to a mode control signal from the configuration register to configure use of the secondary interface in a retransmit mode or a write data receive mode.

15. The method according to claim 14 , further comprising:
in the retransmit mode, retransmitting signals received by the primary interface to the second DRAM IC chip via the secondary interface.

16. The method according to claim 14 , further comprising:
transferring signals with the second IC chip via the primary interface when the secondary interface is configured in the retransmit mode.

17. The method according to claim 16 , wherein the second IC chip is embodied as a memory controller IC chip.

Assignees

• Rambus Inc

Inventors

• Ware Frederick A
• Amirkhany Amir
• Rajan Suresh
• Hekmat Mohammad
• Patil Dinesh

Classifications

• G11C7/1093

  Input synchronization · CPC title

• G11C7/1021

  Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address · CPC title

• G06F13/4068

  Electrical coupling · CPC title

• G11C7/10

  Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers · CPC title

• G11C7/1012

  Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating · CPC title