Three-dimensional semiconductor device and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-12490494-B2
Application number	US-202217834527-A
Country	US
Kind code	B2
Filing date	Jun 7, 2022
Priority date	Nov 29, 2021
Publication date	Dec 2, 2025
Grant date	Dec 2, 2025

Abstract

Disclosed are a three-dimensional semiconductor device and a method of fabricating the same. The semiconductor device includes: a first active region on a substrate, the first active region including a pair of lower source/drain regions and a lower channel structure; a second active region on the first active region, the second active region including a pair of upper source/drain regions and an upper channel structure; and a gate electrode on the lower and upper channel structures. The gate electrode includes: first and second metal structures, which are respectively provided adjacent bottom and top surfaces of semiconductor layers of the lower and upper channel structures.

First claim

What is claimed is:

1 . A three-dimensional semiconductor device, comprising:
a first active region on a substrate, the first active region comprising a pair of lower source/drain regions and a lower channel structure between the pair of lower source/drain regions; a second active region on the first active region, the second active region comprising a pair of upper source/drain regions and an upper channel structure between the pair of upper source/drain regions; and a gate electrode on the lower channel structure and the upper channel structure, wherein the lower channel structure comprises a plurality of lower semiconductor layers, which are spaced apart from each other along a direction perpendicular to an upper surface of the substrate, wherein the upper channel structure comprises a plurality of upper semiconductor layers spaced apart from each other along the direction, wherein the gate electrode comprises:
a first metal structure comprising a first metal and enclosing at least one of the plurality of lower semiconductor layers; and
a second metal structure comprising a second metal and enclosing at least one of the plurality of upper semiconductor layers,
wherein the first metal structure is provided adjacent to a bottom surface of one of an uppermost layer among the plurality of lower semiconductor layers and a lowermost layer among the plurality of upper semiconductor layers, and wherein the second metal structure is provided adjacent to a top surface of the one of the uppermost layer and the lowermost layer.

2 . The device of claim 1 , wherein the plurality of lower semiconductor layers connect the pair of lower source/drain regions to each other, and
wherein the plurality of upper semiconductor layers connect the pair of upper source/drain regions to each other.

3 . The device of claim 1 , wherein the at least one of the plurality of upper semiconductor layers overlaps with the pair of lower source/drain regions along a second direction parallel to the upper surface of the substrate.

4 . The device of claim 3 , wherein a number of the plurality of lower semiconductor layers is smaller than a number of the plurality of upper semiconductor layers.

5 . The device of claim 4 , wherein a current of a transistor of the first active region is smaller than a current of a transistor of the second active region.

6 . The device of claim 1 , wherein the at least one of the plurality of lower semiconductor layers overlaps with the pair of upper source/drain regions along a second direction parallel to the upper surface of the substrate.

7 . The device of claim 6 , wherein a number of the plurality of upper semiconductor layers is smaller than a number of the plurality of lower semiconductor layers.

8 . The device of claim 7 , wherein a current of a transistor of the second active region is smaller than a current of a transistor of the first active region.

9 . The device of claim 1 , further comprising a dummy channel structure between the lower channel structure and the upper channel structure,
wherein the dummy channel structure comprises at least one semiconductor layer that is spaced apart from the pair of lower source/drain regions and the pair of upper source/drain regions.

10 . The device of claim 1 , wherein the first active region is an NMOSFET region,
wherein the second active region is a PMOSFET region, wherein the first metal is an n-type metal, and wherein the second metal is a p-type metal.

11 . A three-dimensional semiconductor device, comprising:
a plurality of lower semiconductor layers on a substrate and spaced apart from each other along a direction perpendicular to an upper surface of the substrate; a lower source/drain region connected to the plurality of lower semiconductor layers; a lower gate electrode on the plurality of lower semiconductor layers; layers, a plurality of upper semiconductor layers spaced apart from each other along the direction on the plurality of lower semiconductor layers; an upper source/drain region connected to the plurality of upper semiconductor layers; and a dummy channel structure between the plurality of lower semiconductor layers and the plurality of upper semiconductor layers, wherein the dummy channel structure comprises at least one semiconductor layer that is spaced apart from the lower source/drain region and the upper source/drain region, wherein the lower gate electrode comprises a first metal structure comprising a first metal and enclosing at least one of the plurality of lower semiconductor layers, and wherein a number of semiconductor layers in the plurality of lower semiconductor layers that are enclosed by the first metal structure, is smaller than a number of the plurality of lower semiconductor layers connected to the lower source/drain region.

12 . The device of claim 11 , further comprising:
an upper gate electrode on the plurality of upper semiconductor layers, wherein the lower gate electrode and the upper gate electrode are connected to each other and constitute a single gate electrode, wherein the upper gate electrode comprises a second metal structure comprising a second metal and enclosing at least one of the plurality of upper semiconductor layers, and wherein a number of semiconductor layers included in the plurality of upper semiconductor layers that are enclosed by the second metal structure, is equal to a number of the plurality of upper semiconductor layers connected to the upper source/drain region.

13 . The device of claim 12 , wherein the first metal structure is adjacent to a bottom surface of an uppermost one of the plurality of lower semiconductor layers, and the second metal structure is adjacent to a top surface of the uppermost one of the plurality of lower semiconductor layers.

14 . The device of claim 11 , wherein the first metal structure is adjacent to a bottom surface of at least one of the plurality of lower semiconductor layers and is omitted from a top surface of the at least one of the plurality of lower semiconductor layers.

15 . The device of claim 11 , wherein the plurality of lower semiconductor layers comprise a first semiconductor layer and a second semiconductor layer,
wherein the lower gate electrode comprises:
a first portion interposed between the substrate and the first semiconductor layer;
a second portion interposed between the first semiconductor layer and the second semiconductor layer; and
a third portion on the second semiconductor layer,
wherein the first portion comprises the first metal structure, and wherein the first metal structure is omitted from the third portion.

16 . A three-dimensional semiconductor device, comprising:
a first active region on a substrate, the first active region comprising a lower channel structure and a lower source/drain region connected to the lower channel structure; a second active region on the first active region, the second active region comprising an upper channel structure and an upper source/drain region connected to the upper channel structure; and a gate electrode on the lower channel structure and the upper channel structure, wherein a center portion of the lower source/drain region has a first thickness, wherein a center portion of the upper source/drain region has a second thickness different from the first thickness, wherein each of the lower source/drain region and the upper source/drain region comprises a first vertex on a side surface, which protrudes in a first direction, and a second vertex, which is an inflection point defined by the side surface

Assignees

• Samsung Electronics Co Ltd

Inventors

• Park Sungil
• Park Jae Hyun
• Ha Daewon

Classifications

• H10D64/0134

  with a treatment, e.g. annealing, after the formation of the insulator and before the formation of the conductor · CPC title

• H10D64/311

  Gate electrodes for field-effect devices · CPC title

• H10D62/81

  of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/6735

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title