Integrated circuit devices including a back side power distribution network structure and methods of forming the same

Patent metadata

Field	Value
Publication number	US-12490491-B2
Application number	US-202318160341-A
Country	US
Kind code	B2
Filing date	Jan 27, 2023
Priority date	Sep 21, 2022
Publication date	Dec 2, 2025
Grant date	Dec 2, 2025

Abstract

Integrated circuit devices and methods of forming the same are provided. The methods may include providing a substrate structure including a substrate, a bottom insulator and a semiconductor region between the substrate and the bottom insulator, the semiconductor region extending in a first direction; forming first and second preliminary transistor structures on the bottom insulator, wherein and the bottom insulator may include first and second portions that the first and second preliminary transistor structures respectively overlap, and a third portion between the first and second portions; replacing the third portion of the bottom insulator with a bottom semiconductor layer; forming a source/drain region between the first and second preliminary transistor structures; replacing the substrate and the semiconductor region with a backside insulator; forming a power contact in the backside insulator, wherein the source/drain region may overlap the power contact; and forming a power rail.

First claim

What is claimed is:

1 . A method of forming an integrated circuit device, the method comprising:
providing a substrate structure including a substrate, a bottom insulator on the substrate and a semiconductor region between the substrate and the bottom insulator, the semiconductor region extending in a first direction; forming first and second preliminary transistor structures on the bottom insulator, wherein the first and second preliminary transistor structures are spaced apart from each other in the first direction, and the bottom insulator comprises first and second portions that the first and second preliminary transistor structures respectively overlap, and a third portion between the first and second portions; replacing the third portion of the bottom insulator with a bottom semiconductor layer; forming a source/drain region between the first and second preliminary transistor structures and on the bottom semiconductor layer; replacing the substrate and the semiconductor region with a backside insulator; forming a power contact in the backside insulator, wherein the source/drain region overlaps the power contact; and forming a power rail, wherein the power contact is between the source/drain region and the power rail.

2 . The method of claim 1 , wherein replacing the third portion of the bottom insulator with the bottom semiconductor layer comprises:
forming a bottom opening in the bottom insulator by removing the third portion of the bottom insulator using the first and second preliminary transistor structures as a mask, wherein the bottom opening exposes the semiconductor region; and forming the bottom semiconductor layer in the bottom opening, wherein the bottom semiconductor layer contacts the semiconductor region.

3 . The method of claim 2 , wherein forming the bottom semiconductor layer in the bottom opening comprises growing the bottom semiconductor layer using the semiconductor region as a seed layer.

4 . The method of claim 2 , wherein the first preliminary transistor structure comprises a first side surface facing the second preliminary transistor structure, and the second preliminary transistor structure comprises a second side surface facing the first preliminary transistor structure,
the method further comprises forming first and second gate liners respectively on the first and second side surfaces, and wherein the third portion of the bottom insulator is removed using the first and second preliminary transistor structures and the first and second gate liners are used as the mask.

5 . The method of claim 1 , further comprising replacing the bottom semiconductor layer with a portion of the backside insulator,
wherein forming the power contact in the backside insulator comprises:
forming a backside opening that extends through the bottom insulator and the backside insulator and exposes a lower surface of the source/drain region; and
forming the power contact that is in the backside opening and contacts the source/drain region.

6 . The method of claim 5 , wherein the lower surface of the source/drain region has a first width in the first direction, an interface between the source/drain region and the power contact has a second width in the first direction, and the first width is wider than the second width.

7 . The method of claim 1 , wherein forming the power contact in the backside insulator comprises:
forming a backside opening that extends through the backside insulator and exposes the bottom semiconductor layer; and forming the power contact that is in the backside opening and contacts the bottom semiconductor layer, wherein the bottom semiconductor layer contacts a lower surface of the source/drain region.

8 . The method of claim 7 , wherein the lower surface of the source/drain region has a first width in the first direction, an interface between the source/drain region and the bottom semiconductor layer has a third width in the first direction, and the first width is wider than the third width.

9 . The method of claim 1 , wherein a width of the power contact in the first direction increases as a distance from the source/drain region increases.

10 . The method of claim 1 , further comprising, before replacing the substrate and the semiconductor region with the backside insulator, forming a back-end-of-line (BEOL) structure including a conductive wire on the source/drain region.

11 . A method of forming an integrated circuit device, the method comprising:
providing a substrate structure including a semiconductor region and a bottom insulator on the semiconductor region; forming first and second preliminary transistor structures that are on the bottom insulator and are spaced apart from each other in a first direction, the bottom insulator comprising first and second portions that the first and second preliminary transistor structures respectively overlap, and a third portion between the first and second portions; replacing the third portion of the bottom insulator with a bottom semiconductor layer; forming a source/drain region between the first and second preliminary transistor structures, wherein a lower surface of the source/drain region contacts the bottom semiconductor layer; forming a power contact, wherein an upper surface of the power contact faces the lower surface of the source/drain region; and forming a power rail on a lower surface of the power contact.

12 . The method of claim 11 , wherein replacing the third portion of the bottom insulator with the bottom semiconductor layer comprises:
forming a bottom opening in the bottom insulator by removing the third portion of the bottom insulator using the first and second preliminary transistor structures as a mask, wherein the bottom opening exposes the semiconductor region; and forming the bottom semiconductor layer in the bottom opening, wherein the bottom semiconductor layer contacts the semiconductor region.

13 . The method of claim 11 , further comprising replacing the bottom semiconductor layer and the semiconductor region with a backside insulator,
wherein forming the power contact comprises:
forming a backside opening that extends through the bottom insulator and the backside insulator and exposes the lower surface of the source/drain region; and
forming the power contact that is in the backside opening and contacts the source/drain region.

14 . The method of claim 11 , further comprising replacing the semiconductor region with a backside insulator,
wherein forming the power contact comprises:
forming a backside opening that extends through the backside insulator and exposes the bottom semiconductor layer; and
forming the power contact that is in the backside opening and contacts the bottom semiconductor layer, wherein the bottom semiconductor layer contacts the lower surface of the source/drain region.

15 . The method of claim 11 , further comprising, before forming the power contact, forming a back-end-of-line (BEOL) structure including a conductive wire on the source/drain region.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Jongjin
• Kim Tae Sun
• Hong Wonhyuk
• Yun Seungchan
• Seo Kang-Ill

Classifications

• H10W20/427

  Power or ground buses · CPC title

• H10W20/481

  on the rear surfaces of the wafers or substrates · CPC title

• H10W20/069 Primary

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10D64/01

  Manufacture or treatment · CPC title

• H10D62/121

  oriented parallel to substrates · CPC title