Nitride-based semiconductor device and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-12490490-B2
Application number	US-202117440203-A
Country	US
Kind code	B2
Filing date	Jul 16, 2021
Priority date	Jul 16, 2021
Publication date	Dec 2, 2025
Grant date	Dec 2, 2025

Abstract

A semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a source electrode and a drain electrode, a gate structure, a first passivation layer, a second passivation layer and a field plate. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer. The source electrode, the drain electrode, and the gate structure are disposed above the second nitride-based semiconductor layer. The first passivation layer is disposed above the second nitride-based semiconductor layer and covers the gate structure. The second passivation layer is disposed above the first passivation layer and in a region between the source and drain electrodes. The field plate is disposed above the second passivation layer and in the region between the source electrode and drain electrode, in which the field plate contacts at least one enclosed air gap above the first passivation layer.

First claim

The invention claimed is:

1 . A nitride-based semiconductor device, comprising:
a first nitride-based semiconductor layer; a second nitride-based semiconductor layer disposed on the first nitride-based semiconductor layer and having a bandgap greater than a bandgap of the first nitride-based semiconductor layer; a source electrode and a drain electrode disposed above the second nitride-based semiconductor layer; a gate structure disposed above the second nitride-based semiconductor layer and in a region between the source electrode and the drain electrode; a first passivation layer disposed above the second nitride-based semiconductor layer and above the gate structure; a second passivation layer disposed above the first passivation layer and in the region between the source electrode and the drain electrode; a field plate disposed above the second passivation layer and in the region between the source electrode and the drain electrode; and a third passivation layer disposed above the field plate, wherein the first passivation layer defines a bottom boundary of at least one enclosed air gap, the second passivation layer defines a first side boundary of the at least one enclosed air gap, the third passivation layer defines a second side boundary of the at least one enclosed air gap, and the field plate defines a top boundary of the at least one enclosed air gap.

2 . The semiconductor device of claim 1 , wherein the second passivation layer is spaced apart from the third passivation layer to define the at least one enclosed air gap therebetween.

3 . The semiconductor device of claim 2 , wherein the at least one enclosed air gap is between the gate structure and the field plate.

4 . The semiconductor device of claim 2 , wherein the at least one enclosed air gap is between the gate structure and the drain electrode.

5 . The semiconductor device of claim 2 , wherein the at least one enclosed air gap comprises a first enclosed air gap and a second enclosed air gap, wherein the first enclosed air gap is between the gate structure and the field plate and the second enclosed air gap is between the gate structure and the drain electrode and in a position lower than the first enclosed air gap.

6 . The semiconductor device of claim 5 , wherein the first enclosed air gap has a width less than a width of the second enclosed air gap.

7 . The semiconductor device of claim 2 , wherein at least one of the first side boundary or the second side boundary of the at least one enclosed air gap is curved.

8 . The semiconductor device of claim 2 , wherein the third passivation layer comprises a dielectric between the at least one enclosed air gap and the drain electrode.

9 . The semiconductor device of claim 2 , wherein the third passivation layer covers the source electrode and the drain electrode.

10 . The semiconductor device of claim 1 , wherein the second passivation layer is shorter than the field plate.

11 . The semiconductor device of claim 1 , wherein the first passivation layer and the second passivation layer have different materials.

12 . The semiconductor device of claim 1 , wherein the second passivation layer climbs to a position higher than the gate structure so as to form a step profile.

13 . The semiconductor device of claim 12 , wherein the field plate is conformal with the second passivation layer.

14 . The semiconductor device of claim 1 , wherein the at least one enclosed air gap comprises a first enclosed air gap and a second enclosed air gap, and the second passivation layer has two opposite ends directly contacting the first enclosed air gap and the second enclosed air gap, respectively.

15 . A method for manufacturing a semiconductor device, comprising:
forming a first nitride-based semiconductor layer on a substrate; forming a second nitride-based semiconductor layer on the first nitride-based semiconductor layer, the second nitride-based semiconductor layer having a bandgap greater than a bandgap of the first nitride-based semiconductor layer; forming a source electrode and a drain electrode disposed above the second nitride-based semiconductor layer; forming a gate structure above the second nitride-based semiconductor layer and in a region between the source electrode and the drain electrode; forming a first passivation layer above the second nitride-based semiconductor layer and above the gate structure; forming a second passivation layer above the first passivation layer and in the region between the source electrode and the drain electrode; forming a blanket conductive layer on the second passivation layer; patterning the blanket conductive layer into a field plate disposed above the second passivation layer and in the region between the source electrode and the drain electrode; removing portions of the second passivation layer such that the second passivation layer becomes narrower than the field plate; and forming a third passivation layer to cover the first passivation layer and the field plate to form at least one enclosed air gap adjacent with the second passivation layer, wherein the first passivation layer defines a bottom boundary of the at least one enclosed air gap, the second passivation layer defines a first side boundary of the at least one enclosed air gap, and the third passivation layer defines a second side boundary of the at least one enclosed air gap.

16 . The method of claim 15 , wherein the removing the portions of the second passivation layer is performed by an etching process using an etchant.

17 . The method of claim 16 , wherein the first passivation layer and the second passivation layer have different materials such that the first passivation layer and the second passivation layer have different etching rate with respect to the etchant.

18 . The method of claim 15 , wherein the removing the portions of the second passivation layer is performed such that the second passivation layer has an end surface directly above the gate structure.

19 . The method of claim 15 , wherein the forming the third passivation layer is performed such that two opposite end surfaces of the field plate are covered by the third passivation layer.

Assignees

• Innoscience Suzhou Technology Holding Co Ltd

Inventors

• Du Weixing
• You Jheng-Sheng

Classifications

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title

• H10W74/137

  the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence) · CPC title

• H10W74/147

  the encapsulations being multilayered · CPC title

• H10D30/475 Primary

  having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs · CPC title

• H10D30/015

  of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT · CPC title