Codeword synchronization method, receiver, network device, and network system

Patent metadata

Field	Value
Publication number	US-12489555-B2
Application number	US-202318494427-A
Country	US
Kind code	B2
Filing date	Oct 25, 2023
Priority date	Apr 26, 2021
Publication date	Dec 2, 2025
Grant date	Dec 2, 2025

Abstract

This application relates to a codeword synchronization method, a chip, a network device, and a system. The codeword synchronization method includes: receiving a first data sequence, where the first data sequence includes a plurality of bits, and a codeword in the first data sequence includes extension information for verifying the codeword; selecting at least one group of bits from the plurality of bits as the extension information to perform verification, and determining a candidate bit in the plurality of bits based on a result of the verification; and determining a synchronization position based on the candidate bit, where the synchronization position indicates a start position of the codeword that is in the first data sequence.

First claim

What is claimed is:

1 . A codeword synchronization method, wherein the method comprises:
receiving a first data sequence, wherein the first data sequence comprises a plurality of bits, and a codeword in the first data sequence comprises extension information for verifying the codeword; selecting at least one group of bits from the plurality of bits as the extension information to perform verification, and determining a candidate bit in the plurality of bits based on a result of the verification; determining multiple second test data blocks in the first data sequence based on the candidate bit, wherein a length of an interval between a position of the candidate bit and a start position of the multiple second test data blocks is an integer multiple of the length of the codeword that is in the first data sequence; and verifying a characteristic value of the multiple second test data blocks, and when the verification succeeds, determining the position of the candidate bit as a synchronization position.

2 . The method according to claim 1 , wherein the selecting at least one group of bits from the plurality of bits as the extension information to perform the verification, and determining the candidate bit in the plurality of bits based on the result of the verification comprises:
determining the candidate bit from among the plurality of bits based on a result of the verification of the extension information and a characteristic value of at least one group of first test data blocks in the first data sequence, wherein each group of the at least one group of first test data blocks comprises multiple first test data blocks, and wherein an interval between a start position of each first test data block in a first group of the at least one group of first test data blocks and the candidate bit is an integer multiple of the length of the codeword.

3 . The method according to claim 2 , wherein the method further comprises:
determining a synchronization possibility index of each group of the at least one group of first test data blocks based on the result of the verification of the extension information and characteristic values of the at least one group of first test data blocks.

4 . The method according to claim 1 , wherein the method further comprises:
selecting at least one group of bits from the multiple second test data blocks as the extension information to perform verification, and when both the verification of the extension information and the verification of the characteristic value succeed, determining the position of the candidate bit as the synchronization position.

5 . The method according to claim 1 , wherein the first data sequence comprises a first subsequence and a second subsequence, the second subsequence is partially the same as, or different from the first subsequence, the candidate bit is comprised in the first subsequence, and the multiple second test data blocks are comprised in the second subsequence.

6 . The method according to claim 1 , wherein the characteristic value comprises:
a quantity of test data blocks determined as correct codewords; a quantity of all-zero sequences in a syndrome; a quantity of zero elements in the syndrome; a quantity of error-correctable test data blocks; or a quantity of test data blocks that pass recheck, wherein in the test data blocks that pass the recheck, a first bit set obtained based on first k bits of the codeword in the first data sequence is the same as original parity bits of the test data blocks, the first k bits of the codeword in the first data sequence are information bits, and k is an integer; or the characteristic value comprises:
a quantity of test data blocks determined as incorrect codewords;
a quantity of non-all-zero sequences in the syndrome;
a quantity of non-zero elements in the syndrome;
a quantity of error-uncorrectable test data blocks; or
a quantity of test data blocks that fail recheck, wherein in the test data blocks that fail the recheck, a first bit set obtained based on the first k bits is different from original parity bits of the test data blocks, the first k bits of the codeword in the first data sequence are information bits, and k is an integer.

7 . The method according to claim 1 , further comprising after the determining the position of the candidate bit as a synchronization position:
receiving a second data sequence, wherein the second data sequence comprises a plurality of bits; determining a synchronization position of the second data sequence based on the synchronization position of the first data sequence, wherein the synchronization position of the second data sequence indicates a start position of a codeword that is in the second data sequence; determining, based on the synchronization position of the second data sequence, whether the second data sequence is in a loss-of-lock state; and in response to a case in which the second data sequence is in the loss-of-lock state, determining an updated synchronization position of the second data sequence.

8 . The method according to claim 7 , wherein the method further comprises:
receiving a third data sequence, wherein the third data sequence comprises a plurality of bits; and in response to the case in which the second data sequence is in the loss-of-lock state, determining an updated synchronization position of the third data sequence.

9 . The method according to claim 8 , wherein a codeword in the third data sequence comprises extension information for verifying the codeword, and determining the updated synchronization position of the third data sequence comprises:
selecting at least one group of bits from the plurality of bits comprised in the third data sequence as the extension information to perform verification, and determining a candidate bit in the third data sequence based on a result of the verification, wherein the candidate bit in the third data sequence is located in the plurality of bits comprised in the third data sequence; and determining the updated synchronization position of the third data sequence based on the candidate bit in the third data sequence.

10 . The method according to claim 1 , wherein the extension information is for performing an additional check on the codeword to enhance performance of the codeword.

11 . The method according to claim 1 , wherein the extension information is comprised in information bits of the codeword, or the extension information is comprised in parity bits of the codeword.

12 . The method according to claim 1 , wherein the first data sequence is a linear block code.

13 . The method according to claim 1 , wherein verifying the characteristic value of the multiple second test data blocks comprises:
sequentially accumulating a characteristic value of each of the multiple second test data blocks to obtain a cumulative value, wherein the verification is successful when the cumulative value meets a synchronization condition.

14 . The method according to claim 1 , wherein the extension information is for performing a parity check or a cyclic redundancy check (CRC) check.

15 . A chip configured to:
receive a first data sequence, wherein the first data sequence comprises a plurality of bits, and a codeword in the first data sequence comprises extension information for verifying the codeword; select at least one group of bits from the plurality of bits as the extension information to perform verification, and determine a candidate bit in the plurality of bits based on a result of the verification; determine multiple second test data blocks in the first data sequence based

Assignees

• Huawei Tech Co Ltd

Inventors

• He Xiang
• Ren Hao

Classifications

• H03M5/145

  Conversion to or from block codes or representations thereof · CPC title

• H04L1/0045 Primary

  Arrangements at the receiver end · CPC title

• H04L7/048

  using the properties of error detecting or error correcting codes, e.g. parity as synchronisation signal · CPC title

• H04L1/0061

  Error detection codes · CPC title

• H04L1/0057 Primary

  Block codes (H04L1/0061, H04L1/0064 take precedence) · CPC title