Forward error correction synchronization

Patent metadata

Field	Value
Publication number	US-2016149595-A1
Application number	US-201414548929-A
Country	US
Kind code	A1
Filing date	Nov 20, 2014
Priority date	Nov 20, 2014
Publication date	May 26, 2016
Grant date	—

Abstract

Techniques for forward error correction synchronization are described herein. The techniques include receiving a bit stream over a transmission link and determining a starting location of a first code word within the bit stream. Determining the starting location of the first code word includes identifying an error correction block associated with a previously received second code word, and designating a bit subsequent to the error correction block as the starting location of the first code word.

First claim

What is claimed is:

1 . A computer implemented method for forward error correction synchronization, comprising:
receiving a bit stream over a transmission link; determining a starting location of a first code word within the bit stream, wherein determining the starting location of the first code word comprises:
identifying an error correction block associated with a previously received second code word; and
designating a bit subsequent to the error correction block as the starting location of the first code word.

2 . The computer implemented method of claim 1 , wherein the error detection block is a checksum for verifying data integrity of the second code word.

3 . The computer implemented method of claim 1 , wherein the designated bit is immediately subsequent to the error correction block.

4 . The computer implemented method of claim 1 , wherein identifying the error correction block comprises:
detecting one of two known data patterns associated with code words comprising the first and second code word; and detecting an unknown data pattern associated with the error correction block.

5 . The computer implemented method of claim 4 , wherein the known data patterns are data patterns present after waking up a transmission link.

6 . The computer implemented method of claim 5 , wherein the known data patterns comprise data patterns associated with transmission link states comprising:
an idle state; a low idle state; or any combination thereof.

7 . The computer implemented method of claim 6 , further comprising bypassing scrambling of the bit stream until synchronization is complete.

8 . An apparatus, comprising logic, at least partially comprising hardware logic of a transmission link, wherein the logic is to:
receive a bit stream; determine a starting location of a first code word within the bit stream, wherein determining the starting location of the first code word comprises:
identifying an error correction block associated with a previously received second code word; and
designating a bit subsequent to the error correction block as the starting location of the first code word.

9 . The apparatus of claim 8 , wherein the error detection block is a checksum for verifying data integrity of the second code word.

10 . The apparatus of claim 8 , wherein the designated bit is immediately subsequent to the error correction block.

11 . The apparatus of claim 8 , wherein identifying the error correction block comprises:
detecting one of two known data patterns associated with code words comprising the first and second code word; and detecting an unknown data pattern associated with the error correction block.

12 . The apparatus of claim 11 , wherein the known data patterns are data patterns present after waking up a component on a transmission link.

13 . The apparatus of claim 12 , wherein the known data patterns comprise data patterns associated with transmission link states comprising:
an idle state; a low idle state; or any combination thereof.

14 . The apparatus of claim 13 , wherein the logic is further configured to bypass scrambling of the bit stream until synchronization is complete.

15 . A computer program product for forward error correction synchronization, the computer product comprising a computer readable storage medium having program code embodied therewith, the program code executable by a processor to perform a method comprising:
receiving a bit stream; determining a starting location of a first code word within the bit stream, wherein determining the starting location of the first code word comprises:
identifying an error correction block associated with a previously received second code word; and
designating a bit subsequent to the error correction block as the starting location of the first code word.

16 . The computer implemented method of claim 15 , wherein the error detection block is a checksum for verifying data integrity of the second code word.

17 . The computer implemented method of claim 15 , wherein the designated bit is immediately subsequent to the error correction block.

18 . The computer implemented method of claim 15 , wherein identifying the error correction block comprises:
detecting one of two known data patterns associated with code words comprising the first and second code word; and detecting an unknown data pattern associated with the error correction block.

19 . The computer implemented method of claim 18 , wherein the known data patterns are data patterns present after waking up a component on a transmission link, further comprising bypass scrambling of the bit stream until synchronization is complete.

20 . The computer implemented method of claim 19 , wherein the known data patterns comprise data patterns associated with transmission link states comprising:
an idle state; a low idle state; or any combination thereof.

Assignees

• Globalfoundries Inc

Inventors

• Benjamini Yiftach
• Butter Adrian S

Classifications

• G06F11/10 Primary

  Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's · CPC title

• H03M13/2906 Primary

  using block codes (H03M13/2957 takes precedence) · CPC title

• H03M13/333 Primary

  Synchronisation on a multi-bit block basis, e.g. frame synchronisation · CPC title

• H04L1/00

  Arrangements for detecting or preventing errors in the information received {(correcting synchronisation H04L7/00)} · CPC title

• H04L1/004

  by using forward error control (H04L1/0618 takes precedence; coding, decoding or code conversion, for error detection or correction H03M13/00) · CPC title