Monitoring control signals of power switches in a half bridge for motor control or other applications

Patent metadata

Field	Value
Publication number	US-12489387-B2
Application number	US-202318354491-A
Country	US
Kind code	B2
Filing date	Jul 18, 2023
Priority date	Jul 18, 2023
Publication date	Dec 2, 2025
Grant date	Dec 2, 2025

Abstract

In some examples, this disclosure describes a method of controlling a high-side power switch and a low-side power switch arranged in a half bridge configuration. The method may comprise driving the gate of the high-side power switch based on high-side pulse modulation (PM) signals; driving a gate of the low-side power switch based on low-side PM signals; and monitoring the high-side PM signals and the low-side PM signals. The high-side PM signals and the low-side PM signals are configured to turn the high-side power switch and the low-side power switch ON and OFF in a complementary fashion, and monitoring may include: detecting one or more absences of either the high-side PM signals or the low-side PM signals; and generating a fault signal in response to detecting the one or more absences.

First claim

The invention claimed is:

1 . A driver circuit configured to control a high-side power switch and a low-side power switch arranged in a half bridge configuration, the driver circuit comprising:
a high-side driver configured to drive a gate of the high-side power switch based on high-side pulse modulation (PM) signals; a low-side driver configured to drive a gate of the low-side power switch based on low-side PM signals; and a logic circuit configured to monitor the high-side PM signals and the low-side PM signals, wherein the high-side PM signals and the low-side PM signals are configured to turn the high-side power switch and the low-side power switch ON and OFF in a complementary fashion, and wherein the logic circuit is configured to detect one or more absences of either the high-side PM signals or the low-side PM signals and generate a fault signal in response to detecting the one or more absences, wherein to detect the one or more absences of either the high-side PM signals or the low side PM signals, the logic circuit comprises a state machine configured to detect low-to-high transitions of the high-side PM signals or the low side PM signals.

2 . The driver circuit of claim 1 , wherein the logic circuit is configured to communicate the fault signal to a processor.

3 . The driver circuit of claim 1 ,
wherein the high-side driver is configured to generate high-side PM drive signals based on high-side PM control signals output from a digital core, wherein the low-side driver is configured to generate low-side PM drive signals based on low-side PM control signals output from the digital core, and wherein the logic circuit is configured to monitor PM control signals and detect the one or more absences of either the high-side PM signals or the low-side PM signals based on monitoring the PM control signals.

4 . The driver circuit of claim 3 , wherein the PM control signals comprise input signals from a processor to the digital core.

5 . The driver circuit of claim 3 , wherein the PM control signals comprise the high-side PM control signals output from the digital core to the high-side driver and the low-side PM control signals output from the digital core to the low-side driver.

6 . The driver circuit of claim 1 , further comprising a level shifter circuit,
wherein the high-side driver is configured to generate high-side PM drive signals based on high-side PM control signals output from a digital core, wherein the low-side driver is configured to generate low-side PM drive signals based on low-side PM control signals output from the digital core, wherein the level shifter circuit is configured to generate level shifted versions of the high-side PM drive signals and the low-side PM drive signals, and wherein the logic circuit is configured to monitor the level shifted versions of the high-side PM drive signals and the low-side PM drive signals and detect the one or more absences of either the high-side PM signals or the low-side PM signals based on monitoring the level shifted versions of the high-side PM drive signals and the low-side PM drive signals.

7 . The driver circuit of claim 1 , wherein the logic circuit includes a counter configured to count successive absences of either the high-side PM signals or the low-side PM signals and generate the fault signal in response to a count value of the counter reaching a count threshold.

8 . The driver circuit of claim 7 , wherein the count threshold is greater than 1 and less than 8.

9 . The driver circuit of claim 8 , wherein the count threshold is 3.

10 . The driver circuit of claim 1 , further comprising a plurality of high-side drivers and a plurality of low-side drivers configured to control a plurality of half bridges.

11 . The driver circuit of claim 10 , wherein the plurality of half bridges is configured to control a multi-phase electric motor.

12 . The driver circuit of claim 11 , wherein for each of the plurality of half bridges, the driver circuit includes a respective logic circuit configured to detect one or more absences of either the high-side PM signals or the low-side PM signals for a respective one of the plurality of half bridges and generate the fault signal in response to detecting the one or more absences.

13 . A method of controlling a high-side power switch and a low-side power switch arranged in a half bridge configuration, the method comprising:
driving a gate of the high-side power switch based on high-side pulse modulation (PM) signals; driving a gate of the low-side power switch based on low-side PM signals; and monitoring the high-side PM signals and the low-side PM signals, wherein the high-side PM signals and the low-side PM signals are configured to turn the high-side power switch and the low-side power switch ON and OFF in a complementary fashion, and wherein monitoring includes: detecting one or more absences of either the high-side PM signals or the low-side PM signals, wherein detecting the one or more absences of either the high-side PM signals or the low side PM signals includes detecting, via a state machine, low-to-high transitions of the high-side PM signals or the low side PM signals; and generating a fault signal in response to detecting the one or more absences.

14 . The method of claim 13 , further comprising:
communicating the fault signal to a processor.

15 . The method of claim 13 ,
wherein a high-side driver is configured to generate high-side PM drive signals based on high-side PM control signals output from a digital core, wherein a low-side driver is configured to generate low-side PM drive signals based on low-side PM control signals output from the digital core, and wherein monitoring the high-side PM signals and the low-side PM signals includes monitoring PM control signals and detecting the one or more absences of either the high-side PM signals or the low-side PM signals based on monitoring the PM control signals.

16 . The method of claim 13 ,
wherein a high-side driver is configured to generate high-side PM drive signals based on high-side PM control signals output from a digital core, wherein a low-side driver is configured to generate low-side PM drive signals based on low-side PM control signals output from the digital core, wherein a level shifter circuit is configured to generate level shifted versions of the high-side PM drive signals and the low-side PM drive signals, and wherein monitoring the high-side PM signals and the low-side PM signals includes monitoring the level shifted versions of the high-side PM drive signals and the low-side PM drive signals and detecting the one or more absences of either the high-side PM signals or the low-side PM signals based on monitoring the level shifted versions of the high-side PM drive signals and the low-side PM drive signals.

17 . The method of claim 13 , further comprising:
maintaining a count value indicative of successive absences of either the high-side PM signals or the low-side PM signals; and generating the fault signal in response to the count value reaching a count threshold.

18 . The method of claim 17 , wherein the count threshold is greater than 1 and less than 6.

19 . The method of claim 13 , wherein the method comprises a method of controlling a plurality of high-side drivers and a plurality of low-side drivers configured to control a plurality of half bridges, wherein the plurality of half bridges is configured to control a multi-phase electric motor.

20 . The method of

Assignees

• Infineon Technologies Ag

Inventors

• Murtaza Diana Raluca
• Murtaza Cristian
• Stemplinger Peter

Classifications

• H03K19/017545

  Coupling arrangements; Impedance matching circuits · CPC title

• H03K2217/0063

  High side switches, i.e. the higher potential [DC] or life wire [AC] being directly connected to the switch and not via the load · CPC title

• H03K2217/0072

  Low side switches, i.e. the lower potential [DC] or neutral wire [AC] being directly connected to the switch and not via the load · CPC title

• H03K17/6874

  in a symmetrical configuration · CPC title

• G01R31/327

  Testing of circuit interrupters, switches or circuit-breakers · CPC title