Semiconductor package with balanced impedance

Patent metadata

Field	Value
Publication number	US-12489040-B2
Application number	US-202217903512-A
Country	US
Kind code	B2
Filing date	Sep 6, 2022
Priority date	Sep 6, 2022
Publication date	Dec 2, 2025
Grant date	Dec 2, 2025

Abstract

A semiconductor package includes a substrate including a die pad, first and second discrete transistor dies mounted on the die pad, an encapsulant body that encapsulates the first and second discrete transistor dies, and a plurality of leads that are exposed from the encapsulant body, wherein the first and second discrete transistor dies are connected in parallel with one another by electrical interconnections that electrically connect common terminals of the first and second discrete transistor dies to one of the leads, and wherein at least one of the electrical interconnections has a balanced configuration that provides substantially identical electrical impedance as between the common terminals of the first and second discrete transistor dies and the lead to which they are connected.

First claim

The invention claimed is:

1 . A semiconductor package, comprising:
a substrate comprising a die pad; first and second discrete transistor dies mounted on the die pad; an encapsulant body that encapsulates the first and second discrete transistor dies; and a plurality of leads that are exposed from the encapsulant body, wherein the first and second discrete transistor dies are connected in parallel with one another by electrical interconnections that electrically connect common terminals of the first and second discrete transistor dies to one of the leads, and wherein at least one of the electrical interconnections has a balanced configuration that provides substantially identical electrical impedance as between the common terminals of the first and second discrete transistor dies and the lead to which they are connected, wherein each of the first and second discrete transistor dies comprise:
first load terminals that face and electrically connect with the die pad; and
second load terminals and gate terminals that face away from the die pad,
wherein the plurality of leads comprises a first DC voltage lead, a second DC voltage lead, and a gate lead, and wherein the electrical interconnections comprise:
a gate connection that connects the gate terminals of the first and second discrete transistor dies with the gate lead; a first DC voltage connection that connects the first load terminals of the first and second discrete transistor dies with the first DC voltage lead; and a second DC voltage connection that connects the second load terminals of the first and second discrete transistor dies with the second DC voltage lead, and wherein one or more of the gate connection, the first DC voltage connection, and the second DC voltage connection has the balanced configuration,
wherein the second DC voltage connection comprises first and second elongated rails that form a u-shaped geometry, and wherein the second DC voltage connection has the balanced configuration, wherein the semiconductor package further comprises:
a first electrical interconnection between the first rail and the second load terminal of the first discrete transistor die; and
a second electrical interconnection between the second rail and the second load terminal of the second discrete transistor die,
wherein the first and second electrical interconnections have substantially identical electrical impedance.

2 . The semiconductor package of claim 1 , wherein the substrate comprises a base pad of electrically isolating material and a structured metallization layer disposed on the base pad, and wherein the die pad is formed in the structured metallization layer.

3 . The semiconductor package of claim 2 , wherein the structured metallization layer comprises a gate distribution pad that is arranged within the die pad, and wherein the gate connection has the balanced configuration.

4 . The semiconductor package of claim 3 , wherein the gate connection comprises:
a common interconnect element connected between the gate lead and the gate distribution pad; and first and second interconnect elements connected between the gate distribution pad and the gate terminals of the first and second discrete transistor dies, respectively, and wherein the first and second interconnect elements have substantially identical electrical impedance.

5 . The semiconductor package of claim 4 , further comprising third and fourth discrete transistor dies mounted on the die pad, wherein the third and fourth discrete transistor dies each comprise first load terminals that face and electrically connect with the die pad and second load terminals and gate terminals that face away from the die pad, wherein the gate connection connects the gate terminals of the third and fourth discrete transistor dies with the gate lead, and wherein the gate connection provides substantially identical electrical impedance as between the gate terminals of the first, second, third and fourth discrete transistor dies and the gate lead.

6 . The semiconductor package of claim 1 , wherein the first DC voltage connection has the balanced configuration.

7 . The semiconductor package of claim 1 , wherein the substrate comprises a base pad of electrically isolating material and the die pad is provided by a single layer of metal which is the only metal region on an upper surface of the base pad.

8 . The semiconductor package of claim 7 , wherein the semiconductor package comprises a lead frame, wherein the lead frame is configured such that the gate lead is part of a continuous metal structure that comprises an internal runner that extends across an edge side of the substrate, and wherein the gate connection comprises interconnect elements connected between the gate terminals of the first and second discrete transistor dies and the internal runner.

9 . A semiconductor package, comprising:
a substrate comprising a die pad of metal; first and second discrete transistor dies mounted on the die pad, each of the first and second discrete transistor dies comprising first load terminals that face and electrically connect with the die pad and second load terminals and gate terminals that face away from the die pad; a gate lead that is electrically connected to the gate terminals of the first and second transistor dies; a first DC voltage lead that is electrically connected to the first load terminals from the first and second discrete transistor dies via the die pad; and a second DC voltage lead that is electrically connected to the second load terminals from the first and second discrete transistor dies, wherein the second DC voltage lead is part of a continuous second DC voltage structure that extends over the substrate and comprises an internal second DC connection span, wherein the internal second DC connection span comprises a planar section that is spaced apart from each of the transistor dies and depressions that protrude away from the planar section, and wherein the depressions are in direct ohmic contact with the second load terminals from the first and second discrete transistor dies.

10 . The semiconductor package of claim 9 , wherein the substrate comprises a base pad of electrically insulating material and the die pad is provided by a single layer of metal which is the only metal region on an upper surface of the base pad.

11 . The semiconductor package of claim 9 , wherein the electrical connection between the gate lead and the gate terminals of the first and second transistor dies has a balanced configuration that provides substantially identical electrical impedance as between the gate terminals of the first and second discrete transistor dies and the gate lead.

12 . The semiconductor package of claim 9 , further comprising a press-fit connector attached to one or both of the continuous second DC voltage structure and the continuous gate metal structure.

13 . The semiconductor package of claim 9 , wherein the second DC voltage lead is part of a continuous second DC voltage structure that extends over the substrate and comprises first and second elongated rails, and wherein the first and second elongated rails directly overlap with the die pad.

14 . The semiconductor package of claim 13 , wherein the electrical connection between the second DC voltage lead and the second load terminals of the first and second transistor dies has a balanced configuration that provides substantially identical electrical impedance as between the second load terminals of the first and second transistor dies and the second DC voltage lead.

15 . The semiconductor package

Assignees

• Infineon Technologies Austria Ag

Inventors

• Luniewski Peter
• Neubert Markus
• Fuegl Michael
• Jakobi Waldemar
• Leipenat Michael
• Lamminger Egbert

Classifications

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W74/111

  the semiconductor body being completely enclosed · CPC title

• H10W70/481

  for devices being provided for in groups H10D8/00 - H10D48/00 · CPC title

• H10W70/411

  Chip-supporting parts, e.g. die pads · CPC title

• H10W90/00

  Package configurations · CPC title