Array substrate and manufacturing method thereof, and display panel
US-2020105799-A1 · Apr 2, 2020 · US
US12484379B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-12484379-B2 |
| Application number | US-202217972112-A |
| Country | US |
| Kind code | B2 |
| Filing date | Oct 24, 2022 |
| Priority date | Dec 24, 2021 |
| Publication date | Nov 25, 2025 |
| Grant date | Nov 25, 2025 |
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An electroluminescent display apparatus may include a first semiconductor pattern including a first channel region and a first conductive region which is a region other than the first channel region, a first gate electrode overlapping the first channel region of the first semiconductor pattern with a first gate insulation layer therebetween, a first interlayer insulation layer covering the first semiconductor pattern, and the first gate electrode, a second semiconductor pattern disposed on the first interlayer insulation layer, the second semiconductor pattern including a second channel region and a second conductive region which is a region other than the second channel region, and a second gate electrode overlapping the second channel region of the second semiconductor pattern with a second gate insulation layer therebetween. The first conductive region of the first semiconductor pattern partially overlaps the second conductive region of the second semiconductor pattern with the first interlayer insulation layer therebetween.
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What is claimed is: 1 . An electroluminescent display apparatus comprising: a first semiconductor pattern disposed on a substrate, the first semiconductor pattern including a first channel region and a first conductive region which is a region other than the first channel region; a first gate electrode overlapping the first channel region of the first semiconductor pattern with a first gate insulation layer therebetween; a data line directly connected to the first conductive region of the first semiconductor pattern without a contact hole; a first interlayer insulation layer covering the first semiconductor pattern and the first gate electrode; a second semiconductor pattern disposed on the first interlayer insulation layer, the second semiconductor pattern including a second channel region and a second conductive region which is a region other than the second channel region; and a second gate electrode overlapping the second channel region of the second semiconductor pattern with a second gate insulation layer therebetween, wherein the first conductive region of the first semiconductor pattern partially overlaps the second conductive region of the second semiconductor pattern with the first interlayer insulation layer therebetween. 2 . The electroluminescent display apparatus of claim 1 , further comprising a storage capacitor connected to the first conductive region of the first semiconductor pattern and the second conductive region of the second semiconductor pattern. 3 . The electroluminescent display apparatus of claim 2 , wherein a first electrode of the storage capacitor is a portion of the first conductive region of the first semiconductor pattern partially overlapping the second conductive region of the second semiconductor pattern with the first interlayer insulation layer therebetween, and a second electrode of the storage capacitor is a portion of the second conductive region of the second semiconductor pattern partially overlapping the first conductive region of the first semiconductor pattern with the first interlayer insulation layer therebetween. 4 . The electroluminescent display apparatus of claim 1 , further comprising a reference voltage line directly connected to the second conductive region of the second semiconductor pattern without a contact hole. 5 . The electroluminescent display apparatus of claim 1 , further comprising: a second interlayer insulation layer covering the second semiconductor pattern, the second gate electrode, and the first interlayer insulation layer; a third semiconductor pattern disposed on the second interlay insulation layer, the third semiconductor pattern including a third channel region and a third conductive region which is a region other than the third channel region; and a third gate electrode overlapping the third channel region of the third semiconductor pattern with a third gate insulation layer therebetween. 6 . The electroluminescent display apparatus of claim 5 , further comprising a power line directly connected to the third conductive region of the third semiconductor pattern. 7 . The electroluminescent display apparatus of claim 5 , wherein a portion of the second conductive region of the second semiconductor pattern overlaps the third channel region of the third semiconductor pattern. 8 . The electroluminescent display apparatus of claim 7 , wherein the electroluminescent display apparatus is configured to apply a fixed voltage having a certain level to the second conductive region of the second semiconductor pattern. 9 . The electroluminescent display apparatus of claim 1 , further comprising a gate line extending from the second gate electrode on the second gate insulation layer, wherein the gate line is connected to the first gate electrode through a first contact hole passing through the second gate insulation layer and the first interlayer insulation layer. 10 . The electroluminescent display apparatus of claim 1 , further comprising: a first gate line extending from the first gate electrode on the first gate insulation layer; and a second gate line extending from the second gate electrode on the second gate insulation layer. 11 . The electroluminescent display apparatus of claim 6 , further comprising: a third interlayer insulation layer covering the third semiconductor pattern, the third gate electrode, the power line, and the second interlayer insulation layer; and a first conductive connection pattern disposed on the third interlayer insulation layer, wherein the first conductive connection pattern is connected to the second conductive region of the second semiconductor pattern through a second contact hole passing through the second interlayer insulation layer and the third interlayer insulation layer and is connected to the third conductive region of the third semiconductor pattern through a third contact hole passing through the third interlayer insulation layer. 12 . The electroluminescent display apparatus of claim 11 , further comprising: an organic insulation layer covering the first conductive connection pattern and the third interlayer insulation layer; and a light emitting device connected to the first conductive connection pattern through a pixel contact hole passing through the organic insulation layer. 13 . The electroluminescent display apparatus of claim 6 , further comprising: a third interlayer insulation layer covering the third semiconductor pattern, the third gate electrode, the power line, and the second interlayer insulation layer; and a second conductive connection pattern disposed on the third interlayer insulation layer, wherein the second conductive connection pattern is connected to the third gate electrode through a fourth contact hole passing through the third interlayer insulation layer and is connected to the first conductive region of the first semiconductor pattern through a fifth contact hole passing through the first interlayer insulation layer, the second interlayer insulation layer, and the third interlayer insulation layer. 14 . The electroluminescent display apparatus of claim 5 , wherein the first conductive region of the first semiconductor pattern, the second conductive region of the second semiconductor pattern, and the third conductive region of the third semiconductor pattern overlap one another partially. 15 . The electroluminescent display apparatus of claim 5 , wherein the first conductive region of the first semiconductor pattern is exposed by the first gate electrode and the first gate insulation layer, the second conductive region of the second semiconductor pattern is exposed by the second gate electrode and the second gate insulation layer, and the third conductive region of the third semiconductor pattern is exposed by the third gate electrode and the third gate insulation layer. 16 . The electroluminescent display apparatus of claim 1 , further comprising a reference voltage line directly connected to the second conductive region of the second semiconductor pattern. 17 . The electroluminescent display apparatus of claim 16 , further comprising a power line directly connected to the third conductive region of the third semiconductor pattern. 18 . The electroluminescent display apparatus of claim 16 , wherein the first interlayer insulation layer covers the data line.
integrated with passive devices, e.g. auxiliary capacitors · CPC title
Interconnections, e.g. scanning lines · CPC title
wherein the TFTs are in active matrices · CPC title
the pixel elements being capacitors · CPC title
Interconnections, e.g. wiring lines or terminals · CPC title
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