Display device

Patent metadata

Field	Value
Publication number	US-2020006401-A1
Application number	US-201916361135-A
Country	US
Kind code	A1
Filing date	Mar 21, 2019
Priority date	Jun 29, 2018
Publication date	Jan 2, 2020
Grant date	—

Abstract

A display device includes: a first electrode layer; a semiconductor layer including a source region, a drain region, and a channel region, wherein at least a portion of the source region or the drain region overlaps the first electrode layer; a second electrode layer arranged adjacent to the channel region; a third electrode layer overlapping the second electrode layer and at least a portion of the source region or the drain region; and a power line electrically connected to the first electrode layer and the third electrode layer.

First claim

What is claimed is:

1 . A display device comprising:
a first electrode layer; a semiconductor layer comprising a source region, a drain region, and a channel region, wherein at least a portion of the source region or the drain region overlaps the first electrode layer; a second electrode layer arranged corresponding to the channel region; a third electrode layer overlapping the second electrode layer and at least a portion of the source region or the drain region; and a power line electrically connected to the first electrode layer and the third electrode layer.

2 . The display device of claim 1 , wherein the first electrode layer overlaps the channel region.

3 . The display device of claim 1 , wherein the first electrode layer is disposed on a lower layer of the semiconductor layer, and
the third electrode layer is disposed on an upper layer of the semiconductor layer.

4 . The display device of claim 1 , wherein the power line receives a substantially constant voltage.

5 . The display device of claim 1 , wherein the channel region of the semiconductor layer is curved.

6 . The display device of claim 1 , further comprising:
a first insulating layer disposed between the first electrode layer and the semiconductor layer; a second insulating layer disposed between the semiconductor layer and the second electrode layer; a third insulating layer disposed between the second electrode layer and the third electrode layer; and a fourth insulating layer disposed between the third electrode layer and the power line.

7 . A display device comprising:
a first driving transistor in a first pixel region of a substrate and having a first semiconductor layer and a first gate electrode, wherein the first semiconductor layer comprises a first source region, a first drain region, and a first channel region; a second driving transistor in a second pixel region adjacent to the first pixel region of the substrate and having a second semiconductor layer and a second gate electrode, wherein the second semiconductor layer comprises a second source region, a second drain region, and a second channel region; a first electrode layer facing at least a portion of the first source region or the first drain region; a second electrode layer facing the first gate electrode and at least a portion of the first source region or the first drain region; a third electrode layer facing at least a portion of the second source region or the second drain region; a fourth electrode layer facing the second gate electrode and at least a portion of the second source region or the second drain region; and a power line electrically connected to the first electrode layer, second electrode layer, third electrode layer, and fourth electrode layer.

8 . The display device of claim 7 , wherein an area of the third electrode layer that overlaps the second source region or the second drain region is greater than an area of the first electrode layer that overlaps the first source region or the first drain region.

9 . The display device of claim 8 , wherein an area of the second source region or the second drain region that overlaps the third electrode layer is greater than an area of the first source region or the first drain region that overlaps the first electrode layer.

10 . The display device of claim 7 , wherein an area of the fourth electrode layer that overlaps the second source region or the second drain region is greater than an area of the second electrode layer that overlaps the first source region or the first drain region.

11 . The display device of claim 10 , wherein an area of the second source region or the second drain region that overlaps the fourth electrode layer is greater than an area of the first source region or the first drain region that overlaps the second electrode layer.

12 . The display device of claim 10 , wherein an area of the fourth electrode layer is greater than an area of the second electrode layer.

13 . The display device of claim 7 , further comprising:
a third driving transistor in a third pixel region adjacent to the second pixel region of the substrate and having a third semiconductor layer and a third gate electrode, wherein the third semiconductor layer comprises a third source region, a third drain region, and a third channel region; a fifth electrode layer overlapping at least a portion of the third source region or the third drain region; and a sixth electrode layer overlapping the third gate electrode and at least a portion of the third source region or the third drain region, wherein the fifth electrode layer and the sixth electrode layer are electrically connected to the power line.

14 . The display device of claim 13 , wherein an area of the fifth electrode layer that overlaps the third source region or the third drain region is equal to an area of the first electrode layer that overlaps the first source region or the first drain region.

15 . The display device of claim 13 , wherein an area of the fifth electrode layer that overlaps the third source region or the third drain region is equal to an area of the third electrode layer that overlaps the second source region or the second drain region.

16 . A display device comprising:
a first driving transistor disposed in a first pixel region of the substrate, and having a first semiconductor layer and a first gate electrode, a first capacitor and a second capacitor, wherein the first semiconductor layer comprises a first source region and a first drain region, the first capacitor comprises a first lower electrode and a first upper electrode and the second capacitor comprises a second lower electrode and a second upper electrode; and a power line electrically connected to the first upper electrode and the second lower electrode, wherein the first lower electrode and the second upper electrode are portions of the first source region or the first drain region, the first upper electrode is disposed on an upper layer of the first semiconductor layer, and the second lower electrode is disposed on a lower layer of the first semiconductor layer.

17 . The display device of claim 16 , wherein the second lower electrode overlaps a channel region of the first semiconductor layer.

18 . The display device of claim 16 , wherein the first pixel circuit further comprises a third capacitor having a third lower electrode and a third upper electrode,
wherein the third upper electrode is electrically connected to the power line, and the third lower electrode is a portion of the first gate electrode.

19 . The display device of claim 16 , further comprising:
a second driving transistor disposed in a second pixel region adjacent to the first pixel region of the substrate and having a second semiconductor layer and a second gate electrode, the second semiconductor layer comprises a second source region and a second drain region; and a second pixel circuit in a second pixel region adjacent to the first pixel region of the substrate, and having a second driving transistor comprising a second semiconductor layer and a second gate electrode, a fourth capacitor and a fifth capacitor, wherein the second semiconductor layer comprises a second source region and a second drain region, the fourth capacitor comprises a fourth lower electrode and a fourth upper electrode, and the fifth capacitor comprises a fifth lower electrode and a fifth upper electrode, wherein the fourth upper electrode and the fifth lower electrode are electrically connected to the power l

Assignees

• Samsung Display Co Ltd

Inventors

• Hwang Youngin
• Gil Elly
• Kim Sungho
• Kim Eungtaek
• Yang Yongho
• Wang Seongmin
• Lee Jina
• Jo Joohyeon
• Chu Seongbaik

Classifications

• G09G3/3208 Primary

  organic, e.g. using organic light-emitting diodes [OLED] · CPC title

• G09G3/3266

  Details of drivers for scan electrodes · CPC title

• G09G3/3225

  using an active matrix · CPC title

• H01L27/1222

  Electricity · mapped topic

• H01L27/3276

  Electricity · mapped topic