Display apparatus and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-12484304-B2
Application number	US-202418419366-A
Country	US
Kind code	B2
Filing date	Jan 22, 2024
Priority date	Aug 14, 2020
Publication date	Nov 25, 2025
Grant date	Nov 25, 2025

Abstract

A display apparatus includes: a substrate including a first area, and a second area adjacent to the first area; a plurality of first pixel circuits at the first area of the substrate, each of the plurality of first pixel circuits including a silicon-based transistor, and an oxide-based transistor; a plurality of second pixel circuits at the second area of the substrate, the plurality of second pixel circuits including transistors; a first shielding layer at the first area, the first shielding layer including a shielding pattern overlapping with the silicon-based transistor of each of the plurality of first pixel circuits; and a second shielding layer at the second area, the second shielding layer including a first through-hole between adjacent second pixel circuits from among the plurality of second pixel circuits. The first shielding layer and the second shielding layer include different materials from each other.

First claim

What is claimed is:

1 . A method of manufacturing a display apparatus, the method comprising:
forming a plurality of first pixel circuits at a first area of a substrate, each of the plurality of first pixel circuits comprising a silicon-based transistor and an oxide-based transistor; forming a plurality of second pixel circuits at a second area of the substrate that is adjacent to the first area, the plurality of second pixel circuits comprising transistors; forming a first shielding layer at the first area, the first shielding layer comprising a shielding pattern overlapping with the silicon-based transistor of each of the plurality of first pixel circuits; forming a second shielding layer at the second area, the second shielding layer comprising a first through-hole between adjacent second pixel circuits from among the plurality of second pixel circuits; and forming a third shielding layer at the second area, the third shielding layer comprising a second through-hole overlapping with the first through-hole of the second shielding layer, wherein the forming of the first shielding layer, the forming of the second shielding layer, and the forming of the third shielding layer use a same mask.

2 . The method of claim 1 , wherein the forming of the first shielding layer, the second shielding layer, and the third shielding layer by using the same mask comprises:
forming a first material layer on the substrate; forming a second material layer on the first material layer; forming a first photoresist pattern on the second material layer, the first photoresist pattern comprising a first portion having a first thickness, and a second portion having a second thickness greater than the first thickness; forming the first shielding layer and the third shielding layer by removing portions of the first material layer and the second material layer by using the first photoresist pattern as a mask; forming a second photoresist pattern by removing the first photoresist pattern by the first thickness; forming the second shielding layer by additionally removing a portion of the second material layer by using the second photoresist pattern as a mask; and removing the second photoresist pattern.

3 . The method of claim 2 , wherein the first portion of the first photoresist pattern is at the first area of the substrate, and has an isolated shape, and
wherein the second portion of the first photoresist pattern is at the second area of the substrate, and comprises a pattern hole overlapping with the first through-hole and the second through-hole.

4 . The method of claim 2 , wherein the forming of the first material layer comprises:
forming an amorphous silicon layer on the substrate; and doping impurities into the amorphous silicon layer.

5 . The method of claim 2 , wherein the second material layer comprises a metal material.

6 . The method of claim 1 , wherein the second shielding layer and the third shielding layer overlap with transistors of the second pixel circuits.

7 . The method of claim 1 , further comprising forming a buffer layer on the first shielding layer, the second shielding layer, and the third shielding layer.

Assignees

• Samsung Display Co Ltd

Inventors

• Choi Kyunghyun
• Ko Moosoon
• Jung Jingoo
• Jung Sugwoo

Classifications

• H10K59/65

  OLEDs integrated with inorganic image sensors · CPC title

• H10K59/12 Primary

  Active-matrix OLED [AMOLED] displays · CPC title

• H10K59/8792

  comprising light absorbing layers, e.g. black layers · CPC title

• H10K59/1201

  Manufacture or treatment · CPC title

• H10K59/1213

  the pixel elements being TFTs · CPC title