Thin film transistor, display device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-10199507-B2
Application number	US-201314011920-A
Country	US
Kind code	B2
Filing date	Aug 28, 2013
Priority date	Dec 3, 2012
Publication date	Feb 5, 2019
Grant date	Feb 5, 2019

Abstract

A thin film transistor and a method of manufacturing the same, and a display device and a method of manufacturing the same are disclosed, in which the thin film transistor substrate comprises an active layer formed on a substrate; a gate electrode controlling electron transfer within the active layer; a source electrode connected with one end area of the active layer; a drain electrode connected with the other end area of the active layer; and a light-shielding layer formed under the active layer to shield light from entering the active layer.

First claim

What is claimed is:

1. A thin film transistor substrate, comprising:
a substrate;
a light-shielding layer disposed on and in direct contact with the substrate;
a gate electrode disposed on and in direct contact with the light-shielding layer;
a gate insulating film disposed on and in direct contact with the gate electrode;
an active layer disposed on and in direct contact with the gate insulating film, the active layer having depressed end portions such that an upper surface of the depressed end portion is at least at a same level or higher as an upper surface of the gate insulating film over the gate electrode, the active layer having an area greater than that of the gate electrode, the gate electrode controlling electron transfer within the active layer;
a channel protective member directly on a channel area of the active layer, the channel protective member having an area smaller than that of the active area and of the gate electrode;
a source electrode connected with and disposed over one end area of the active layer, and over the gate insulating film;
a drain electrode connected with and disposed over the other end area of the active layer, and over the gate insulating film; and
an insulating interlayer disposed over the channel protective member and under the source electrode and the drain electrode to directly contact upper surfaces of the active layer and the gate insulating layer, the source electrode and the drain electrode penetrating the insulating interlayer to directly contact the active layer,
wherein a lateral surface of the source electrode that is disposed on and in direct contact with an upper surface of the insulating interlayer extends laterally beyond a first end of the active layer,
wherein a lateral surface of the drain electrode that is disposed on and in direct contact with the upper surface of the insulating interlayer extends laterally beyond a second end of the active layer,
wherein the light-shielding layer is configured to shield light from entering the active layer,
wherein the light-shielding layer has an area equal to or greater than that of the active layer, and
wherein a surface of an end of at least one of the source electrode and the drain electrode laterally faces a side surface of the first end or the second end of the active layer.

2. The thin film transistor substrate of claim 1 , wherein the light-shielding layer is made of a semiconductor material or a black resin material.

3. The thin film transistor substrate of claim 2 , wherein the semiconductor material is made of amorphous silicon.

4. The thin film transistor substrate of claim 3 , wherein the amorphous silicon is formed at a thickness of 1000 Å to 3000 Å.

5. The thin film transistor of claim 1 , wherein the insulating interlayer is disposed on and in direct contact with entire upper and side surfaces of the channel protective member.

6. The thin film transistor of claim 1 , further comprising:
a passivation layer on the source and drain electrode; and
a pixel electrode connected to the drain electrode through the passivation layer,
wherein an upper surface of the insulating interlayer has a stepped shape corresponding to upper surfaces of the gate insulating layer, the active layer, and the channel protective member, and
wherein the passivation layer and the pixel electrode each have stepped shapes corresponding to the step shape of the upper surface of the insulating interlayer.

7. The thin film transistor of claim 1 , wherein the source electrode and the drain electrode are both formed of a same material at a same level in direct contact with an upper surface of the insulating interlayer.

8. The thin film transistor of claim 1 , wherein the lateral surface of the source electrode is lower than an upper surface at the first end of the active layer, and wherein the lateral surface of the drain electrode is lower than an upper surface at the second end of the active layer.

9. A method of manufacturing a thin film transistor substrate, the method comprising:
forming a substrate;
forming a light-shielding layer on and in direct contact with the substrate;
forming a gate electrode on and in direct contact with the light-shielding layer;
forming a gate insulating film on and in direct contact with the gate electrode;
forming an active layer on and in direct contact with the gate insulating film, the active layer having depressed end portions such that an upper surface of the depressed end portion is at least at a same level or higher as an upper surface of the gate insulating film over the gate electrode, the active layer having an area greater than that of the gate electrode, the gate electrode controlling electron transfer within the active layer;
forming a channel protective member directly on a channel area of the active layer, the channel protective member having an area smaller than that of the active area and of the gate electrode;
forming a source electrode connected with and over one end area of the active layer, and over the gate insulating film;
forming a drain electrode connected with and over the other end area of the active layer, and over the gate insulating film; and
forming an insulating interlayer over the channel protective member and under the source electrode and the drain electrode to directly contact upper surfaces of the active layer and the gate insulating layer, the source electrode and the drain electrode penetrating the insulating interlayer to directly contact the active layer,
wherein a lateral surface of the source electrode that is disposed on and in direct contact with an upper surface of the insulating interlayer extends laterally beyond a first end of the active layer,
wherein a lateral surface of the drain electrode that is disposed on and in direct contact with the upper surface of the insulating interlayer extends laterally beyond a second end of the active layer,
wherein the light-shielding layer is configured to shield light from entering the active layer,
wherein the light-shielding layer has an area equal to or greater than that of the active layer, and
wherein a surface of an end of at least one of the source electrode and the drain electrode laterally faces a side surface of the first end or the second end of the active layer.

10. The method of claim 9 , wherein the light-shielding layer is made of a semiconductor material or a black resin material.

11. The method of claim 9 , wherein the light-shielding layer and the gate electrode are patterned together by one mask process.

12. The method of claim 9 , wherein the insulating interlayer is disposed on and in direct contact with entire upper and side surfaces of the channel protective member.

13. The method of claim 9 , further comprising:
a passivation layer on the source and drain electrode; and
a pixel electrode connected to the drain electrode through the passivation layer,
wherein an upper surface of the insulating interlayer has a stepped shape corresponding to upper surfaces of the gate insulating layer, the active layer, and the channel protective member, and
wherein the passivation layer and the pixel electrode each have stepped shapes corresponding to the step shape of the upper surface of the insulating interlayer.

14. The method of claim 9 , wherein the source electrode and the drain electrode are simultaneously formed of a same material at a same level in direct contact with an upper surface of the insulating interlayer.

15. A display device comprising a thin film transistor substrate, the thin film transistor substrate comprising:
a substrate;
a light-shielding layer di

Assignees

• Lg Display Co Ltd

Inventors

• Jeon Seung Joon
• Cho Ki Sul
• Seo Seong Moh

Classifications

• H01L29/66969

  Electricity · mapped topic

• H01L29/7869 Primary

  Electricity · mapped topic

• H01L29/78633

  Electricity · mapped topic

• H10D99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10D30/6723

  having light shields · CPC title