Printed circuit board

Patent metadata

Field	Value
Publication number	US-12484148-B2
Application number	US-202217742916-A
Country	US
Kind code	B2
Filing date	May 12, 2022
Priority date	Dec 22, 2021
Publication date	Nov 25, 2025
Grant date	Nov 25, 2025

Abstract

A printed circuit board includes: a wiring substrate including a plurality of insulating layers, a plurality of wiring layers, and a plurality of via layers; and a bridge embedded in the wiring substrate and having a plurality of connection pads thereon. An uppermost wiring layer of the plurality of wiring layers includes a plurality of bump pads connected to the plurality of connection pads, and a pitch between at least two adjacent connection pads of the plurality of connection pads is larger than a pitch between at least two adjacent ones of the plurality of bump pads.

First claim

What is claimed is:

1 . A printed circuit board comprising:
a wiring substrate including a plurality of insulating layers, a plurality of wiring layers, and a plurality of via layers; and a bridge embedded in at least one of the plurality of insulating layers of the wiring substrate at a depth such that an upper surface of a body of the bridge is below an upper surface of a wiring layer of the plurality of wiring layers disposed on the at least one of the plurality of insulating layers of the wiring substrate, and having a plurality of connection pads disposed on the upper surface of the body of the bridge, wherein an uppermost wiring layer of the plurality of wiring layers includes a plurality of bump pads connected to the plurality of connection pads, the plurality of connection pads include a row of connection pads spaced apart from each other, the plurality of bump pads include a row of bump pads spaced apart from each other, and each distance between center lines of every two adjacent connection pads of the row of connection pads is larger than each distance between center lines of every two adjacent bump pads of the row of bump pads, the plurality of connection pads have a size greater than the plurality of bump pads.

2 . The printed circuit board of claim 1 , wherein the plurality of insulating layers include a core layer which is thicker than each of other layers of the plurality of insulating layers,
the wiring substrate has a through portion penetrating through the core layer, and the bridge is disposed in the through portion in a face-up form such that the plurality of connection pads face the uppermost wiring layer.

3 . The printed circuit board of claim 2 , wherein the plurality of insulating layers further include a plurality of first and second build-up layers disposed on upper and lower sides of the core layer, respectively, and
at least a portion of the through portion is filled by at least a portion of at least one of the plurality of first and second build-up layers.

4 . The printed circuit board of claim 1 , wherein the plurality of insulating layers include a core layer which is thicker than each of other layers of the plurality of insulating layers,
the wiring substrate has a cavity penetrating through a portion of the core layer, and the bridge is disposed in the cavity in a face-up form such that the plurality of connection pads face the uppermost wiring layer.

5 . The printed circuit board of claim 4 , wherein the plurality of insulating layers further include a plurality of first and second build-up layers disposed on upper and lower sides of the core layer, respectively, and
at least a portion of the cavity is filled by at least a portion of at least one of the plurality of first build-up layers.

6 . The printed circuit board of claim 1 , wherein the bridge includes a coreless substrate.

7 . The printed circuit board of claim 6 , wherein the coreless substrate includes a plurality of resin layers, a plurality of circuit layers, and a plurality of conductor via layers, and an uppermost one of the plurality of circuit layers includes the plurality of connection pads.

8 . The printed circuit board of claim 7 , wherein the plurality of resin layers include an organic insulating material.

9 . The printed circuit board of claim 1 , further comprising a plurality of connection conductors disposed on the plurality of bump pads, respectively, to be connected to the plurality of bump pads, respectively,
wherein each distance between the centers of at least two adjacent connection pads of the plurality of connection pads is larger than each distance between centers of at least two adjacent ones of the plurality of connection conductors.

10 . The printed circuit board of claim 9 , further comprising first and second dies adjacent to each other and each mounted on the wiring substrate through the plurality of connection conductors and connected to each other through the bridge,
wherein the first die includes a logic chip, and the second die includes a memory chip.

11 . The printed circuit board of claim 1 , further comprising a plurality of electrical connection metals each disposed on a lowermost one of the plurality of wiring layers to be connected to the lowermost wiring layer.

Assignees

• Samsung Electro Mech

Inventors

• Lee Jin Uk
• Hwang Chi Won
• Kim Eun Sun

Classifications

• H05K2201/10159

  Memory · CPC title

• H05K1/0298

  Multilayer circuits · CPC title

• H05K1/181

  associated with surface mounted components · CPC title

• H05K1/115

  Via connections; Lands around holes or via connections (H05K1/112 takes precedence) · CPC title

• H05K1/0313

  Organic insulating material · CPC title