Analog-to-digital converter with 3rd order noise transfer function

Patent metadata

Field	Value
Publication number	US-12483264-B2
Application number	US-202318208588-A
Country	US
Kind code	B2
Filing date	Jun 12, 2023
Priority date	Jun 12, 2023
Publication date	Nov 25, 2025
Grant date	Nov 25, 2025

Abstract

A VCO-Based Continuous-Time (CT) delta-sigma modulator (DSM) with a noise-shaping (NS) successive approximation register (SAR) quantizer for a 3rd order noise transfer function (NTF) is presented. An anti-aliasing filter (AAF) enables this new hybrid architecture. The 28 nm CMOS prototype NSQ VCO CTΣΔ achieves 84.2 dB SNDR and 86.8 dB DR within a 1 MHz bandwidth while consuming 1.62 mW at 100 MS/s. The core circuit occupies only 0.024 mm2. No calibration or coefficient tuning is required.

First claim

What is claimed is:

1 . An analog-to-digital converter, comprising:
a voltage controlled oscillator configured to receive an an input voltage and outputs a voltage whose frequency varies according to the input voltage; a quantizer circuit with noise shaping capability; an anti-aliasing filter interconnected between an output of the voltage controlled oscillator and an input of the quantizer circuit; a feedback path from an output of the quantizer to an input of the voltage controlled oscillator; and a clocked-averaging circuit in the feedback path, where the clocked-averaging circuit converts bits from the quantizer to bits encoded with unary coding and shifts the bits with unary coding two bit positions each clock cycle.

2 . The analog-to-digital converter of claim 1 wherein the clocked-averaging circuit includes a barrel shifter circuit having a series of multiplexers.

3 . The analog-to-digital converter of claim 1 exhibits a noise transfer function having third order.

4 . An analog-to-digital converter, comprising:
a voltage controlled oscillator configured to receive an input voltage and outputs a voltage whose frequency varies according to the input voltage; a Johnson counter serially coupled between the voltage controlled oscillator and a phase detector, where the Johnson counter is configured to receive the output from the voltage controlled oscillator and operates to divide frequency of the output received from the voltage controlled oscillator; a quantizer circuit with noise shaping capability; an anti-aliasing filter interconnected between an output of the phase detector and an input of the quantizer circuit, where notches of the anti-aliasing filter align with sampling frequency of the quantizer circuit; a feedback path from an output of the quantizer to an input of voltage controlled oscillator; and a clocked-averaging circuit in the feedback path, where the clocked-averaging circuit converts bits from the quantizer to bits encoded with unary coding and shifts the bits with unary coding two bit positions each clock cycle.

5 . The analog-to-digital converter of claim 4 wherein the anti-aliasing filter includes an integration sampler circuit and an infinite impulse response filter.

6 . The analog-to-digital converter of claim 4 wherein the quantizer circuit operates to convert a continuous analog signal from the anti-aliasing filter into a discrete digital representation using a binary search.

7 . The analog-to-digital converter of claim 4 wherein the quantizer circuit includes a successive approximation register with second order noise shaping.

8 . The analog-to-digital converter of claim 4 wherein the clocked-averaging circuit includes a barrel shifter circuit having a series of multiplexers.

Assignees

• Univ Michigan Regents

Inventors

• Chen Hsiang-Wen
• Flynn Michael P

Classifications

• H03M1/0854 Primary

  of quantisation noise · CPC title

• H03M1/0629

  Anti-aliasing · CPC title

• H03M1/60

  with intermediate conversion to frequency of pulses · CPC title

• H03M1/508 Primary

  the pulse width modulator being of the self-oscillating type · CPC title