Apparatus and method for monitoring duty cycle of memory clock signal

Patent metadata

Field	Value
Publication number	US-12483230-B2
Application number	US-202318454507-A
Country	US
Kind code	B2
Filing date	Aug 23, 2023
Priority date	Dec 8, 2022
Publication date	Nov 25, 2025
Grant date	Nov 25, 2025

Abstract

Disclosed herein are an apparatus and method for monitoring the duty cycle of a memory clock signal. The apparatus for monitoring a duty cycle of a memory clock signal includes a clock frequency converter configured to generate a second monitoring target clock signal by decreasing a frequency of a first monitoring target clock signal while maintaining a duty cycle of the first monitoring target clock signal, and a pulse counter configured to measure a pulse width of the second monitoring target clock signal using a reference clock signal.

First claim

What is claimed is:

1 . An apparatus for monitoring a duty cycle of a memory clock signal, comprising:
a clock frequency converter configured to generate a second monitoring target clock signal by decreasing a frequency of a first monitoring target clock signal while maintaining a duty cycle of the first monitoring target clock signal; and a pulse counter configured to measure a pulse width of the second monitoring target clock signal using the first monitoring target clock signal, wherein the clock frequency converter comprises a plurality of half clock generators connected in cascade, each of the half clock generators being configured to output a clock signal by decreasing a frequency of an input clock signal to half while maintaining a duty cycle of the input clock signal, wherein each of the half clock generators comprises: a clock divider configured to decrease the frequency of the input clock signal to half; a pulse width doubler configured to double a pulse width of the input clock signal; and an AND gate configured to perform a logical AND operation on an output signal of the clock divider and an output signal of the pulse width doubler.

2 . The apparatus of claim 1 , wherein the pulse width doubler comprises:
a capacitor and a reset switch connected in parallel between a first node and a ground terminal; a first current source, wherein a positive terminal of the first current source is connected to a power source; a first switch connected between a negative terminal of the first current source and the first node and turned on/off in response to the first monitoring target clock signal; a second current source, wherein a negative terminal of the second current source is grounded; a second switch connected between a positive terminal of the second current source and the first node and turned on/off in response to an inverted signal of the first monitoring target clock signal; and a comparator, wherein a positive terminal of the comparator is connected to the first node and a negative terminal of the comparator is grounded.

3 . The apparatus of claim 1 , wherein:
the pulse counter includes multiple flip-flops, the second monitoring target clock signal is input as an enable signal of each of the multiple flip-flops, and the first monitoring target clock signal as reference clock signal is input as a clock signal to each of the multiple flip-flops.

4 . A method for monitoring a duty cycle of a memory clock signal, comprising:
generating a second monitoring target clock signal by decreasing a frequency of a first monitoring target clock signal while maintaining a duty cycle of the first monitoring target clock signal; and measuring a pulse width of the second monitoring target clock signal using the first monitoring target clock signal, wherein generating the second monitoring target clock signal comprises: performing a plurality of times an operation of decreasing a frequency of a clock signal to half while maintaining a duty cycle of the clock signal, wherein decreasing the frequency of the clock signal to half while maintaining the duty cycle of the clock signal comprises: generating a first output signal by decreasing the frequency of the clock signal to half; generating a second output signal by doubling a pulse width of the clock signal; and performing a logical AND operation on the first output signal and the second output signal.

5 . A device for converting a frequency of a duty cycle monitoring target clock signal, wherein:
the device is configured to generate a second monitoring target clock signal by decreasing a frequency of a first monitoring target clock signal while maintaining a duty cycle of the first monitoring target clock signal, and the device comprises a plurality of half clock generators connected in cascade, each of the half clock generators being configured to output a clock signal by decreasing a frequency of an input clock signal to half while maintaining a duty cycle of the input clock signal, wherein each of the half clock generators comprises: a clock divider configured to decrease the frequency of the input clock signal to half; a pulse width doubler configured to double a pulse width of the input clock signal; and an AND gate configured to perform a logical AND operation on an output signal of the clock divider and an output signal of the pulse width doubler.

6 . The device of claim 5 , wherein the pulse width doubler comprises:
a capacitor and a reset switch connected in parallel between a first node and a ground terminal; a first current source, wherein a positive terminal of the first current source is connected to a power source; a first switch connected between a negative terminal of the first current source and the first node and turned on/off in response to the first monitoring target clock signal; a second current source, wherein a negative terminal of the second current source is grounded; a second switch connected between a positive terminal of the second current source and the first node and turned on/off in response to an inverted signal of the first monitoring target clock signal; and a comparator, wherein a positive terminal of the comparator is connected to the first node and a negative terminal of the comparator is grounded.

Assignees

• Electronics & Telecommunications Res Inst

Inventors

• Cho Min-Hyung
• Kim Yi-Gyeong
• Park Su-Jin
• Jeon Young-Deuk

Classifications

• H03K5/00006

  Changing the frequency (modulating pulses H03K7/00; frequency dividers H03K21/00 - H03K29/00; additive or subtractive mixing of two pulse rates into one G06F7/605; pulse rate dividers G06F7/68) · CPC title

• H03K5/1565

  the output pulses having a constant duty cycle · CPC title

• H03K5/05

  by the use of clock signals or other time reference signals · CPC title

• H03K5/15066

  using bistable devices (H03K5/15093 takes precedence) · CPC title

• H03K5/131 Primary

  Digitally controlled · CPC title