Apparatuses and methods for a multi-bit duty cycle monitor

Patent metadata

Field	Value
Publication number	US-2020160902-A1
Application number	US-201816198433-A
Country	US
Kind code	A1
Filing date	Nov 21, 2018
Priority date	Nov 21, 2018
Publication date	May 21, 2020
Grant date	—

Abstract

Embodiments of the disclosure are drawn to apparatuses and methods for a multi-bit duty cycle monitor. A clock signal may be provided to a memory in order to synchronize one or more operations of the memory. The clock signal may have a duty cycle which is adjusted by a duty cycle adjustor of the memory. The duty cycle of the adjusted clock signal may be monitored by a multi-bit duty cycle monitor. The multi-bit duty cycle monitor may provide a multi-bit signal which indicates if the duty cycle of the adjusted clock signal is above or below a target duty cycle value (or if the duty cycle is outside tolerances around the target duty cycle). The multi-bit duty cycle monitor may provide the multi-bit signal while access operations of the memory are occurring.

First claim

1 . An apparatus comprising:
a duty cycle adjustor configured to adjust a duty cycle of a clock signal based on a duty code stored in a register; and a duty cycle monitor coupled to the adjusted clock signal and configured to provide a multi-bit signal based on the duty cycle of the clock signal, wherein the multi-bit signal is in a first state if the duty cycle is less than a lower threshold, a second state if the duty cycle is greater than an upper threshold, and a third state if the duty cycle is between the upper threshold and the lower threshold, and wherein the duty code is adjusted based on the state of the multi-bit signal.

2 . The apparatus of claim 1 , wherein the duty cycle monitor comprises a first comparator with a positive offset and a second comparator with a negative offset, wherein the upper threshold is based on the positive offset and wherein the lower threshold is based on the negative offset.

3 . The apparatus of claim 1 , wherein the multi-bit signal comprises a first bit and a second bit, wherein the first state and the second state comprise the first bit and the second bit being a same value, and wherein the third state comprises the first bit and the second bit being different values.

4 . The apparatus of claim 1 , wherein the upper threshold is greater than a target duty cycle and the lower threshold is below the target duty cycle.

5 . The apparatus of claim 1 , wherein the upper threshold and the lower threshold are programmable values.

6 . The apparatus of claim 1 , wherein the duty cycle adjustor is configured to adjust the duty cycle of the clock signal by an amount that is responsive to the multi-bit signal.

7 . The apparatus of claim 1 , wherein the duty cycle adjustor and the duty cycle monitor are components of a memory.

8 . The apparatus of claim 7 , wherein the memory is configured to perform access operations, and wherein the duty cycle monitor is configured to receive the multi-bit signal while the access operations are being performed.

9 . An apparatus comprising:
a first comparator with a first offset, wherein the first comparator provides a first signal; a second comparator with a second offset, wherein the second comparator provides a second signal; a third comparator with a third offset, wherein the third comparator provides a third signal; a first clock signal coupled to a positive input of each of the first, second, and third comparators; and a second clock signal coupled to a negative input of each of the first, second, and third comparators, wherein the first offset is greater than the third offset, and the second offset is between the first and the third offset.

10 . The apparatus of claim 9 , further comprising one or more logic gates configured to generate a two-bit signal responsive to the first signal, the second signal, and the third signal.

11 . The apparatus of claim 10 , wherein the third signal is a first bit of the two-bit signal.

12 . The apparatus of claim 10 , wherein a second bit of the two-bit signal is based on the first signal and the second signal.

13 . The apparatus of claim 9 , wherein the first offset determines an upper threshold and the third offset determines a lower threshold.

14 . An apparatus comprising:
a memory configured to perform access operations based, at least in part, on a clock signal; a duty cycle adjuster configured to adjust the duty cycle of the clock signal based on a duty code; and a duty cycle monitor coupled to the adjusted clock signal and configured to provide a multi-bit signal with a state responsive to the duty cycle of the adjusted clock signal, wherein the state of the multi-bit signal is updated while the access operations are being performed, and wherein the duty code is increased responsive to the multi-bit signal being in a first state, and decreased responsive to the multi-bit signal being in a second state.

15 . The apparatus of claim 14 , further comprising a mode register configured to store the duty code and the multi-bit signal.

16 . The apparatus of claim 15 , wherein the mode registered is configured to store an enable signal, and wherein the duty cycle monitor is activated responsive to the enable signal being in an active state.

17 . The apparatus of claim 15 , further comprising logic coupled to the mode register and configured to adjust a value of the duty code responsive to the state of the multi-bit signal.

18 . The apparatus of claim 14 , wherein the duty code is not changed responsive to the multi-bit signal being in a third state.

19 . The apparatus of claim 18 , wherein the multi-bit signal is in the first state when the duty cycle is above an upper threshold, is in the second state when the duty cycle is below a lower threshold, and is in the third state when the duty cycle is between the upper threshold and the lower threshold.

20 . The apparatus of claim 19 , wherein the duty monitor comprises a first comparator with a first offset and a second comparator with a second offset which is less than the first offset, wherein the upper threshold is based on the first offset and the lower threshold is based on the second offset.

21 . The apparatus of claim 14 , wherein the multi-bit signal comprises a first bit and a second bit, and wherein the first state and the second state of the multi-bit signal comprise the first bit and the second bit having a same logical level.

22 . A method comprising:
performing access operations on a memory device, wherein timing of the access operations is based, at least in part, on a clock signal; adjusting a duty cycle of the clock signal based on a duty code; generating, while performing the access operations, a signal which indicates a direction of adjustment to the duty code based at least in part on the duty cycle of the clock signal and a target duty cycle value.

23 . The method of claim 22 , wherein the signal is a multi-bit signal which indicates that the duty code is below a lower threshold in a first state, above an upper threshold in a second state, and between the upper threshold and the lower threshold in a third state.

24 . The method of claim 22 , further comprising increasing a value of the duty code when the signal is in the first state, decreasing the duty code when the signal is in the second state and keeping the value of the duty code the same when the signal is in the third state.

25 . An apparatus comprising:
a memory device configured to perform access operations based, at least in part, on a clock signal; a first comparator configured to provide a first output with a value based on a duty cycle of the clock signal being above an upper threshold; a second comparator configured to provide a second output with a value based on the duty cycle of the clock signal being above or below a target duty cycle; a third comparator configured to provide a third output with a value based on the duty cycle of the clock signal being below a lower threshold; and a mode register configured to store a state of a multi-bit signal, wherein the state of the multi-bit signal is based on the first output, the second output, and the third output.

26 . The apparatus of claim 25 , wherein the state of the multi-bit signal is updated while the access operations are being performed.

27 . The apparatus of claim 25 , further comprising at least one logic gate coupled to one or more o

Assignees

• Micron Technology Inc

Inventors

• Gans Dean D

Classifications

• G11C11/4076 Primary

  Timing circuits (for regeneration management G11C11/406) · CPC title

• H03K5/1565 Primary

  the output pulses having a constant duty cycle · CPC title

• G11C2207/2254

  Calibration · CPC title

• G11C7/22 Primary

  Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management · CPC title

• G11C7/1045

  Read-write mode select circuits · CPC title