Power amplifier system

Patent metadata

Field	Value
Publication number	US-12483204-B2
Application number	US-202217706985-A
Country	US
Kind code	B2
Filing date	Mar 29, 2022
Priority date	Mar 29, 2022
Publication date	Nov 25, 2025
Grant date	Nov 25, 2025

Abstract

Disclosed is a power amplifier system having a main amplifier with an input coupled to a main radio frequency (RF) input and an output connected to a main RF output, wherein the main amplifier exhibits a nonlinear gain characteristic with compression. At least one compression compensating amplifier has a signal input coupled to the common RF input and a signal output coupled to the common RF output.

First claim

What is claimed is:

1 . A power amplifier system comprising:
a main amplifier having a series stack of p-type transistors with a first signal input and a first signal output and a series stack of n-type transistors having a second signal input coupled to a common radio frequency, RF, input with the first signal input and a second signal output coupled to a common RF output with the first signal output, wherein the main amplifier exhibits a nonlinear gain characteristic with compression; a compression compensating (CC) amplifier having a third signal input coupled to the common RF input and a third signal output coupled to the common RF output, the CC amplifier comprising:
a first p-type transistor coupled in parallel with one of the p-type transistors in the series stack of p-type transistors;
a first n-type transistor coupled in parallel with one of the n-type transistors in the series stack of n-type transistors; and
a class-C bias network having a first p-type bias output coupled to a gate of the first p-type transistor and a first n-type bias output coupled to a gate of the first n-type transistor, wherein the class-C bias network is configured to generate a first p-type class-C bias for the first p-type transistor, and the class-C bias network is further configured to generate a first n-type class-C bias for the first n-type transistor, wherein the first p-type class-C bias generated at the first p-type bias output and the first n-type class-C bias generated at the first n-type bias output are configured to generate an offset bias that aligns an activation of a class-C parallel amplifier with an inflection point of a compression in the main amplifier, wherein an additional gain provided by the compression compensating (CC) amplifier is configured to inversely match the compression of the main amplifier to compensate the compression of the main amplifier.

2 . The power amplifier system of claim 1 , wherein the CC amplifier further comprises an amplitude modulation-phase modulation (AM-PM) compensator configured to maintain substantially constant the input capacitance of the CC amplifier.

3 . The power amplifier system of claim 1 , wherein the compression compensating (CC) amplifier comprises:
a second p-type transistor coupled in parallel with the first p-type transistor; and a second n-type transistor coupled in parallel with the first n-type transistor, wherein the class-C bias network has a second p-type bias output coupled to a gate of the second p-type transistor and a second n-type bias output coupled to a gate of the second n-type transistor, wherein the class-C bias network is configured to generate a second p-type class-C bias for the second p-type transistor, and the class-C bias network is further configured to generate a second n-type class-C bias for the second n-type transistor.

4 . The power amplifier system of claim 3 , wherein the first p-type bias output and the second p-type bias output and first n-type bias output and the second n-type bias output are set at different levels to provide piecewise compensation of an amplitude modulation-amplitude modulation (AM-AM) distortion generated due to soft compression experienced by the main amplifier.

5 . The power amplifier system of claim 3 , wherein the first p-type bias output and the second p-type bias output are set at different levels and the first n-type bias output and the second p-type bias output are also set at different levels to provide piecewise compensation of an AM-AM distortion generated due to soft compression experienced by the main amplifier.

6 . The power amplifier system of claim 5 , wherein the stacked devices comprising n-type devices are replaceable by p-type devices or the stacked devices comprising p-type devices are replaceable by n-type devices.

7 . The power amplifier system of claim 1 , wherein the main amplifier and the CC amplifier are complementary metal oxide semiconductor (CMOS)-type amplifiers.

8 . The power amplifier system of claim 7 , wherein the main amplifier and the CC amplifier are partially depleted silicon-on-insulator (SOI) CMOS-type amplifiers.

9 . The power amplifier system of claim 7 , wherein the main amplifier and the CC amplifier are fully depleted SOI CMOS-type amplifiers.

10 . The power amplifier system of claim 1 , wherein the CC amplifier further includes an input AM-PM compensator configured to provide compensation for input capacitance of the CC amplifier.

11 . The power amplifier system of claim 10 , wherein the input AM-PM compensator is configured to provide a substantially constant input capacitance while the CC amplifier is actively compensating for AM-AM distortion generated by the main amplifier during soft compression.

12 . The power amplifier system of claim 10 , wherein the input AM-PM compensator comprises a field-effect transistor that is configured as a varactor having a bias network to set a threshold where its equivalent capacitance starts decreasing.

13 . The power amplifier system of claim 12 , wherein the input AM-PM compensator further includes a resistor coupled between a fixed voltage node and the field-effect transistor that is configured as a varactor, in order to set the threshold where its equivalent capacitance starts decreasing.

14 . The power amplifier system of claim 1 , further including an output AM-PM compensator realized with a fixed capacitance connected in parallel drain-to-source with a middle transistor in the n-type series stack of transistors, the p-type series stack of transistors, or a complementary-type of series stack of transistors.

15 . The power amplifier system of claim 1 , further including an output AM-PM compensator realized with a varactor capacitance connected in parallel drain-to-source with a middle transistor in the series stack of transistors (n-type, p-type or complementary-type) that presents a larger equivalent capacitance when the middle cascode device is in saturation operation and a smaller equivalent capacitance when the middle cascode device is in triode operation.

16 . The power amplifier system of claim 1 , wherein the main amplifier and the CC amplifier provide an efficiency between 25% and 45% over an output power range between −2.0 dBm and up to 25 dBm.

17 . The power amplifier system of claim 16 , wherein the main amplifier and the CC amplifier draw a peak current that is below 100 mA at a power level of up to 25 dBm.

Assignees

• Qorvo Us Inc

Inventors

• Scott Baker
• Maxim George
• Granger-Jones Marcus

Classifications

• H03F3/211

  using a combination of several amplifiers (H03F3/60 takes precedence) · CPC title

• H03F1/223

  with MOSFET's · CPC title

• H03F2200/451

  the amplifier being a radio frequency amplifier · CPC title

• H03F3/245

  with semiconductor devices only · CPC title

• H03F1/0222

  by using a signal derived from the input signal · CPC title