Hiberate (HIB8) exit time for universal flash storage (UFS) devices by monitoring when to enable or disable low power states without waiting on squelch detection

Patent metadata

Field	Value
Publication number	US-12481509-B2
Application number	US-202318353861-A
Country	US
Kind code	B2
Filing date	Jul 17, 2023
Priority date	Nov 8, 2022
Publication date	Nov 25, 2025
Grant date	Nov 25, 2025

Abstract

Rather than waiting on a squelch to detect the difference in the state from steady to floating, this disclosure suggests using the time from when a reference clock is turned on to begin the process to exit the hibernation state. The reference clock is turned off while a data storage device is in the hibernation state to save power. Once the host is ready for the device to exit the hibernation state, the reference clock is turned on. The reference clock is monitored for the change. Once the reference clock is on, the data storage device returns to a steady state. In the ready state, the data storage device has a shortened ready time. Once the ready time is complete, the data storage device may now exit the hibernation state without waiting on squelch detection or a hibernation exit request from the host.

First claim

What is claimed is:

1 . A data storage device, comprising:
a memory device; and a controller coupled to the memory device, wherein the controller is configured to:
monitor a reference clock while in a hibernation state;
detect that the reference clock has been turned off;
detect that the reference clock signal has been activated by a host device; and
in response to the detection, exit the hibernation state without waiting on squelch detection.

2 . The data storage device of claim 1 , wherein a host transmission (Tx) line is floating at a time of the detection.

3 . The data storage device of claim 1 , wherein a data storage device transmission (Tx) line is floating at a time of the detection.

4 . The data storage device of claim 1 , wherein exiting the hibernation state comprises powering up components of the data storage device.

5 . The data storage device of claim 4 , wherein powering up components comprises a burst on a data storage device transmission (TX) line.

6 . The data storage device of claim 1 , wherein the controller is further configured to inform the host device that the data storage device has exited the hibernation state.

7 . The data storage device of claim 1 , wherein the detecting occurs between about 2 microseconds to about 4 microseconds from a beginning of the clock signal being activated.

8 . The data storage device of claim 1 , wherein the controller is further configured to detect a host device transmission (TX) line has been driven to DIFF_N.

9 . The data storage device of claim 8 , wherein the controller is further configured to drive a data storage device TX line to DIFF_N upon the detecting the host device TX line being driven to DIFF_N.

10 . The data storage device of claim 1 , wherein a data storage device time to activate (T-Activate) is between about 0 seconds and about 10 microseconds.

11 . A data storage device, comprising:
a memory device; and a controller coupled to the memory device, wherein the controller is configured to:
enter a hibernation state at request of a host device, wherein while in the hibernation state a data storage device transmission (Tx) line is floating;
monitor a reference clock while in the hibernation state;
detect that the reference clock has been turned off;
detect that the reference clock signal is activated;
begin to activate data storage device for a data storage device activation time period (T-Activate);
execute a burst on the data storage device TX line; and
inform the host device that the data storage device has exited the hibernation state without waiting on squelch detection.

12 . The data storage device of claim 11 , wherein T-Activate for the data storage device occurs prior to a host device T-Activate.

13 . The data storage device of claim 12 , wherein the data storage device T-Activate is longer than the host device T-Activate.

14 . The data storage device of claim 11 , wherein the data storage device T-Activate begins while a host device Tx line is floating.

15 . The data storage device of claim 11 , wherein the informing occurs less than 100 microseconds after the detecting.

16 . The data storage device of claim 11 , wherein the executing a burst occurs substantially simultaneous with a burst on a host device Tx line.

17 . The data storage device of claim 11 , wherein the data storage device T-Activate is up to about 5 nanoseconds.

18 . A data storage device, comprising:
memory means; and a controller coupled to the memory means, wherein the controller is configured to:
monitor a reference clock while in a hibernation state;
detect that the reference clock has been turned off;
detect a change in a reference clock signal and begin exiting hibernation without waiting on squelch detection, wherein the change in the reference clock is the reference clock being activated;
begin a time to activation (T-Activate) state on a data storage device transmission (Tx) line;
execute a burst on the data storage device Tx line; and
drive the data storage device Tx line to DIFF_N.

19 . The data storage device of claim 18 , wherein the detecting comprises detecting a reference clock signal to exist.

20 . The data storage device of claim 18 , wherein during the detecting the data storage device Tx line is floating.

Assignees

• Sandisk Technologies Inc

Inventors

• Ganon Doron
• Lerner Eitan

Classifications

• G06F1/04

  Generating or distributing clock signals or signals derived directly therefrom · CPC title

• G06F1/3237

  by disabling clock generation or distribution · CPC title

• G06F1/3275

  Power saving in memory, e.g. RAM, cache · CPC title

• G06F9/4418 Primary

  Suspend and resume; Hibernate and awake · CPC title