Apparatus, method, and system for early deep sleep state exit of a processing element

Patent metadata

Field	Value
Publication number	US-9454218-B2
Application number	US-201514659253-A
Country	US
Kind code	B2
Filing date	Mar 16, 2015
Priority date	Dec 21, 2010
Publication date	Sep 27, 2016
Grant date	Sep 27, 2016

Abstract

An apparatus and method is described herein for providing an early wake scheme before spawning a new thread. An early wake indication may be provided an amount of time, which may include an amount of time to perform a demotion from a current power state to a lower power state that is closer to an active power state, before a new thread is to be spawned and executed on a processing element (e.g., core or thread). Upon encountering the spawn of the new thread, such as a helper thread, the processing element may further transition from the lower power state to an active power state. The new thread may be executed on the processing element without incurring the latency associated with execution of the new thread waiting for the demotion from the current power state to an active power state after the spawn of the new thread.

First claim

What is claimed is:

1. A processor comprising:
a first processing element to execute a first thread to generate an early wake indication;
a second processing element to execute a second thread spawned after the early wake indication is generated from the first thread; and
a power control circuit to transition the second processing element from a first power state to a second power state in response to the early wake indication from the first thread and transition the second processing element to an active power state in response to a spawn of the second thread, wherein the first power state and the second power state are lower power consumption states than the active power state.

2. The processor of claim 1 , wherein the power control circuit is to transition the second processing element from the first power state to the second power state an amount of time before the spawn of the second thread, wherein the amount of time includes a time to transition the second processing element from the first power state to the second power state.

3. The processor of claim 1 , wherein the first thread is a main thread and the second thread is a helper thread to return data from the second thread to the first thread.

4. The processor of claim 1 , wherein the early wake indication comprises an update to an interrupt control register and the power control circuit is to transition the second processing element from the first power state to the second power state in response to the update.

5. The processor of claim 1 , wherein the first processing element is a first core and the second processing element is a second core.

6. The processor of claim 1 , wherein the first power state is a first Advanced Configuration and Power Interface (ACPI) non-operating power state, the second power state is a second ACPI non-operating power state, and the active power state is an ACPI operating state.

7. A processor comprising:
a processing element to execute a thread at an active power state;
a circuit to detect a spawn command to spawn the thread and generate an early wake indication before the thread is to be executed; and
a power control circuit to transition the processing element from a first power state to a second power state in response to the early wake indication, wherein the first power state and the second power state are lower power consumption states than the active power state.

8. The processor of claim 7 , wherein the power control circuit is to transition the processing element from the first power state to the second power state an amount of time before a spawn of the thread, wherein the amount of time includes a time to transition the processing element from the first power state to the second power state.

9. The processor of claim 7 , wherein the thread is a helper thread to return data to a main thread.

10. The processor of claim 7 , wherein the early wake indication comprises an update to an interrupt control register and the power control circuit is to transition the processing element from the first power state to the second power state in response to the update.

11. The processor of claim 7 , wherein the processing element is a core.

12. The processor of claim 7 , wherein the first power state is a first Advanced Configuration and Power Interface (ACPI) non-operating power state, the second power state is a second ACPI non-operating power state, and the active power state is an ACPI operating state.

13. A processor comprising:
a processing element to execute a thread at an active power state;
a circuit to detect a call to the thread and generate an early wake indication before the thread is to be executed; and
a power control circuit to transition the processing element from a first power state to a second power state in response to the early wake indication, wherein the first power state and the second power state are lower power consumption states than the active power state.

14. The processor of claim 13 , wherein the power control circuit is to transition the processing element from the first power state to the second power state an amount of time before the call to the thread, wherein the amount of time includes a time to transition the processing element from the first power state to the second power state.

15. The processor of claim 13 , wherein the thread is a helper thread to return data to a main thread.

16. The processor of claim 13 , wherein the early wake indication comprises an update to an interrupt control register and the power control circuit is to transition the processing element from the first power state to the second power state in response to the update.

17. The processor of claim 13 , wherein the processing element is a core.

18. The processor of claim 13 , wherein the first power state is a first Advanced Configuration and Power Interface (ACPI) non-operating power state, the second power state is a second ACPI non-operating power state, and the active power state is an ACPI operating state.

19. An apparatus comprising:
a detection circuit to detect a software generated command with a reference to an early wake value;
a control storage element coupled to the detection circuit, the control storage element to be updated with the early wake value in response to the detection circuit detecting the software generated command; and
a power control circuit coupled to the control storage element, the power control circuit to transition a processing element from a first low power state to a second low power state in response to the control storage element being updated with the early wake value.

20. The apparatus of claim 19 , wherein the detection circuit to detect the software generated command comprises a detection circuit to detect an early wake instruction.

21. The apparatus of claim 19 , wherein the detection circuit to detect the software generated command comprises a detection circuit to detect a write referencing the early wake value to the control storage element.

22. The apparatus of claim 21 , wherein the write referencing the early wake value to the control storage element includes a write to an interrupt command register, and wherein the interrupt command register includes an early wake field to be updated by the early wake value in response to the detection circuit detecting the write referencing the early wake value.

23. The apparatus of claim 19 , wherein the software generated command further includes a reference to a processing element identification value to identify the processing element and the control storage element is to be updated with the processing element identification value, and wherein the power control circuit to transition the processing element from the first low power state to the second low power state in response to the control storage element being updated with the early wake value comprises:
a transmit circuit to transmit an indication of the early wake value to at least the processing element in response to the control storage element being updated with the early wake value and the processing element identification value; and
the power control circuit is to transition the processing element from the first low power state to the second low power state in response to the indication of the early wake value being transmitted to the processing element.

24. The apparatus of claim 19 , wherein the first low power state is a first Advanced Configuration and Power Interface (ACPI) non-opera

Assignees

• Intel Corp

Inventors

• Guddeti Jayakrishna
• Bhattacharyya Binata

Classifications

• G06F1/329 Primary

  by task scheduling · CPC title

• Y02B60/32

  Cross-Sectional Technologies · mapped topic

• G06F13/24

  using interrupt (G06F13/32 takes precedence) · CPC title

• G06F1/3228

  Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands · CPC title

• Y02B60/144

  Cross-Sectional Technologies · mapped topic