Vector maximum and minimum with indexing

Patent metadata

Field	Value
Publication number	US-12481503-B2
Application number	US-202418670855-A
Country	US
Kind code	B2
Filing date	May 22, 2024
Priority date	May 24, 2019
Publication date	Nov 25, 2025
Grant date	Nov 25, 2025

Abstract

A method to compare first and second source data in a processor in response to a vector maximum with indexing instruction includes specifying first and second source registers containing first and second source data, a destination register storing compared data, and a predicate register. Each of the registers includes a plurality of lanes. The method includes executing the instruction by, for each lane in the first and second source register, comparing a value in the lane of the first source register to a value in the corresponding lane of the second source register to identify a maximum value, storing the maximum value in a corresponding lane of the destination register, asserting a corresponding lane of the predicate register if the maximum value is from the first source register, and de-asserting the corresponding lane of the predicate register if the maximum value is from the second source register.

First claim

What is claimed is:

1 . A device, comprising:
a first register configured to store a first set of values; a second register configured to store a second set of values; and a functional unit configured to:
receive an instruction specifying the first register and the second register;
based on the instruction, for each value of the first set of values and a corresponding value of the second set of values,
compare the value of the first set of values to the corresponding value of the second set of values;
identify one of the value of the first set of values and the corresponding value of the second set of values based the comparison; and
store a value in a predicate register to indicate whether the identified value is from the first set of values or the second set of values; and

perform an operation associated with the first set of values and the second set of values based on the values of the predicate register.

2 . The device of claim 1 , wherein the instruction specifies a maximum sorting operation, and wherein the identified value is a greater of the value of the first set of values and the corresponding value of the second set of values.

3 . The device of claim 1 , wherein the instruction specifies a minimum sorting operation, and wherein the identified value is a lesser of the value of the first set of values and the corresponding value of the second set of values.

4 . The device of claim 1 , comprising:
a set of functional units including the functional unit, wherein the instruction specifies the functional unit.

5 . The device of claim 1 , wherein the instruction specifies whether the first set of values and the second set of values are signed or unsigned values.

6 . The device of claim 1 , wherein the instruction specifies the predicate register.

7 . The device of claim 1 , wherein the functional unit is further configured to:
for each value of the first set of values and the corresponding value of the second set of values, store the identified value in the second register.

8 . The device of claim 1 , wherein the functional unit is further configured to:
for each value of the first set of values and the corresponding value of the second set of values, store the identified value in a third register that is different from the first register and the second register.

9 . The device of claim 1 , wherein the first register includes a set of lanes each of which stores a respective value of the first set of values, and wherein the second register includes a set of lanes each of which stores a respective value of the second set of values.

10 . The device of claim 1 , wherein the first register is a 512-bit register, wherein the second register a 512-bit register, and wherein the predicate register is a 64-bit register.

11 . The device of claim 10 , wherein each value of the first set of values is a 8-bit value, wherein each value of the second set of value is a 8-bit value, and wherein each value of the values of the predicate register is a 1-bit value.

12 . The device of claim 1 , wherein the operation is a sorting operation, and wherein to perform the sorting operation, the functional unit is configured to exclude a value of the first set of values or a value of the second set of values from the sorting operation based on the values of the predicate register.

13 . The device of claim 1 , wherein the functional unit is further configured to determine a number of a specific value existing in the values of the predicate register.

14 . The device of claim 1 , wherein the functional unit is further configured to transfer the values of the predicate register to another register.

15 . A system, comprising:
a memory configured to storing instructions including a first instruction, wherein the first instruction specifies a first register storing a first set of values and a second register storing a second set of values; a processor configured to execute the instructions to:
based on the first instruction, for each value of the first set of values and a corresponding value of the second set of values,
compare the value of the first set of values to the corresponding value of the second set of values;
identify one of the value of the first set of values and the corresponding value of the second set of values based the comparison; and
store a value in a third register to indicate whether the identified value is from the first set of values or the second set of values; and

perform an operation associated with the first set of values and the second set of values based on the values of the third register.

16 . The system of claim 15 , wherein the first instruction specifies a maximum sorting operation, and wherein the identified value is a greater of the value of the first set of values and the corresponding value of the second set of values.

17 . The system of claim 15 , wherein the first instruction specifies a minimum sorting operation, and wherein the identified value is a lesser of the value of the first set of values and the corresponding value of the second set of values.

18 . The system of claim 15 , wherein the processor is further configured to:
for each value of the first set of values and the corresponding value of the second set of values, store the identified value in a register.

19 . The system of claim 15 , wherein the operation is a sorting operation, and wherein to perform the sorting operation, the processor is configured to exclude a value of the first set of values or a value of the second set of values from the sorting operation based on the values of the third register.

20 . The system of claim 15 , wherein the processor is further configured to determine a number of a specific value existing in the values of the third register.

Assignees

• Texas Instruments Inc

Inventors

• Bui Duc
• Dent Peter Richard
• Anderson Timothy D

Classifications

• G06F9/3887

  controlled by a single instruction for multiple data lanes [SIMD] · CPC title

• G06F9/30038

  using a mask · CPC title

• G06F9/30018

  Bit or string instructions · CPC title

• G06F9/30036

  Instructions to perform operations on packed data, e.g. vector, tile or matrix operations · CPC title

• G06F9/30105

  Register structure · CPC title