Silicon carbide semiconductor device

Patent metadata

Field	Value
Publication number	US-12477787-B2
Application number	US-202318193888-A
Country	US
Kind code	B2
Filing date	Mar 31, 2023
Priority date	May 26, 2022
Publication date	Nov 18, 2025
Grant date	Nov 18, 2025

Abstract

An active region has, in a periphery thereof, a p-type outer peripheral region that has sequentially from a front surface of a semiconductor substrate, a p ++ -type contact extension portion, a p-type base extension portion, and an upper portion and a lower portion of a p + -type extension portion, so as to form, at an outer end portion thereof, steps that are recessed stepwise toward a center of the active region and that in a depth direction, are arranged in ascending order of proximity thereof to the center. An innermost JTE region configuring a voltage withstanding structure contacts an outer end portion of the contact extension portion. Beneath the JTE region, a p + -type embedded region is provided at a same depth as the lower portion of the extension portion so as to be apart from the JTE region and the outer peripheral region and surround the periphery of the active region.

First claim

What is claimed is:

1 . A silicon carbide semiconductor device, comprising:
a semiconductor substrate containing silicon carbide and having a first main surface and a second main surface that are opposite to each other, an entire area of the first main surface being flat, the semiconductor substrate having an active region in a center of the semiconductor substrate and a termination region that surrounds a periphery of the active region; a first semiconductor region of a first conductivity type, provided in the semiconductor substrate, spanning the active region and the termination region; a second semiconductor region of a second conductivity type, provided between the first main surface and the first semiconductor region, in the active region; a device structure having a pn junction between the first semiconductor region and the second semiconductor region, a current that passes through the pn junction flowing through the device structure; a second-conductivity-type outer peripheral region surrounding the periphery of the active region, the second-conductivity-type outer peripheral region being provided between the first main surface and the first semiconductor region, between the device structure and the termination region; a voltage withstanding structure configured by a plurality of second-conductivity-type voltage withstanding regions, provided between the first main surface and the first semiconductor region, in the termination region, the plurality of second-conductivity-type voltage withstanding regions being provided apart from one another in a direction parallel to the first main surface in concentric shapes surrounding the periphery of the active region; a first electrode electrically connected to the second semiconductor region and the second-conductivity-type outer peripheral region, the first electrode being provided at the first main surface; and a second electrode electrically connected to the first semiconductor region, the second electrode being provided on the second main surface of the semiconductor substrate, wherein the second-conductivity-type outer peripheral region has, at an outer end portion thereof, a plurality of extension portions each extending outward in a radial direction toward an end of the semiconductor substrate and terminating so that in the depth direction from the first main surface, the plurality of extension portions are arranged in descending order of proximity thereof to the end of the semiconductor substrate, thereby forming a plurality of steps that are recessed stepwise from an outer end of the outer end portion toward the center of the semiconductor substrate and in a depth direction from the first main surface, are arranged in ascending order of proximity thereof to the center, the voltage withstanding structure is in contact with an outer end of a first extension portion that is an uppermost one among the plurality of extension portions, the uppermost one being closest to the first main surface among the plurality of extension portions, and the silicon carbide semiconductor device further comprises in the termination region, a second-conductivity-type embedded region surrounding the periphery of the active region, the second-conductivity-type embedded region being provided apart from the voltage withstanding structure and the second-conductivity-type outer peripheral region, at a same depth as a depth of a second extension portion that is a lowermost one among the plurality of extension portions, the lowermost one being closest to the second main surface among the plurality of extension portions.

2 . The silicon carbide semiconductor device according to claim 1 , wherein
the plurality of second-conductivity-type voltage withstanding regions includes a first second-conductivity-type voltage withstanding region, and the second-conductivity-type embedded region faces, in the depth direction, the first second-conductivity-type voltage withstanding region.

3 . The silicon carbide semiconductor device according to claim 2 , wherein
the second-conductivity-type embedded region is positioned closer to the center of the semiconductor substrate than is an outer end portion of the first second-conductivity-type voltage withstanding region.

4 . The silicon carbide semiconductor device according to claim 1 , wherein
an impurity concentration of the second-conductivity-type embedded region is equal to an impurity concentration of the second extension portion.

5 . The silicon carbide semiconductor device according to claim 1 , wherein
an impurity concentration of the second-conductivity-type embedded region is higher than an impurity concentration of the plurality of second-conductivity-type voltage withstanding regions.

6 . The silicon carbide semiconductor device according to claim 1 , wherein
the device structure has:
a plurality of third semiconductor regions of the first conductivity type, electrically connected to the first electrodes, the plurality of third semiconductor regions being selectively formed between the first main surface and the second semiconductor region,
a plurality of trenches penetrating through the plurality of third semiconductor regions and the second semiconductor region and reaching the first semiconductor region,
a plurality of gate electrodes provided in the plurality of trenches, via a plurality of gate insulating films, respectively, and
a plurality of second-conductivity-type high-concentration regions selectively provided between the first semiconductor region and the second semiconductor region so as to be closer to the second main surface than are bottoms of the plurality of trenches, an impurity concentration of the plurality of second-conductivity-type high-concentration regions being higher than an impurity concentration of the second semiconductor region, and
the plurality of extension portions of the second-conductivity-type outer peripheral region further includes third and fourth extension portions, wherein
the third extension portion is a portion of the second semiconductor region, that is disposed closer to the end of the semiconductor substrate than is the device structure, the third extension portion having a first surface and a second surface that are opposite to each other, the second surface of the third extension portion facing the second main surface,
the first extension portion is provided in contact with the third extension portion between the first main surface and the third extension portion, an impurity concentration of the first extension portion being higher than an impurity concentration of the third extension portion,
the fourth extension portion is a first part of the plurality of second-conductivity-type high-concentration regions, that is disposed closer to the end of the semiconductor substrate than is the device structure and faces the first main surface, the fourth extension portion being adjacent to the second surface of the third extension portion, and
the second extension portion is a second part of the plurality of second-conductivity-type high-concentration regions, that is disposed closer to the end of the semiconductor substrate than is the device structure, and is different from the first part, the second extension portion being provided between and in contact with the fourth extension portion and the first semiconductor region.

7 . The silicon carbide semiconductor device according to claim 6 , wherein
bottoms of the plurality of second-conductivity-type voltage withstanding regions are positioned closer to the first main surface than is a bottom of the first extension portion.

8 . The silicon carbide semiconductor device according to claim 6 , wherein
bottoms of the plurality of second-conductivity-

Assignees

• Fuji Electric Co Ltd

Inventors

• Hoshi Yasuyuki

Classifications

• H10D62/8325

  Silicon carbide · CPC title

• H10D30/665

  having edge termination structures · CPC title

• H10D30/0297

  using recessing of the gate electrodes, e.g. to form trench gate electrodes · CPC title

• H10D62/157

  Impurity concentrations or distributions · CPC title

• H10D62/106

  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions · CPC title