Switching device

Patent metadata

Field	Value
Publication number	US-9966460-B2
Application number	US-201715425411-A
Country	US
Kind code	B2
Filing date	Feb 6, 2017
Priority date	Mar 9, 2016
Publication date	May 8, 2018
Grant date	May 8, 2018

Abstract

A switching device includes a semiconductor substrate having a first element range and an ineffective range. First trenches extend in a first direction across the first element range and the ineffective range. Second trenches are provided in each inter-trench region within the first element range and are not provided within the ineffective range. A gate electrode is disposed in the trenches. No contact hole is provided in an interlayer insulating film within the ineffective range. The first metal layer covers the interlayer insulating film. The insulating protective film covers a portion of the first metal layer on its outer peripheral side within the ineffective range. The second metal region is in contact with the first metal layer within an opening of the insulating protective film, and is in contact with a side surface of the opening.

First claim

What is claimed is:

1. A switching device comprising:
a semiconductor substrate including a first element range, and an inactive region disposed between the first element range and an outer peripheral end surface of the semiconductor substrate;
a plurality of first trenches provided in an upper surface of the semiconductor substrate, the plurality of first trenches extending in parallel to each other along a first direction across the first element range and the inactive region, in a plan view of the upper surface of the semiconductor substrate, each region interposed between the first trenches is set as an inter-trench region;
a plurality of second trenches provided in the upper surface in each of the inter-trench regions within the first element range and not provided within the inactive region, the second trenches spaced apart from each other along the first direction, each of the second trenches connected to two of the first trenches, a width of the inactive region in the first direction is greater than a pitch of the second trenches in the first direction,
each of the inter-trench regions within the inactive region including a second conductivity type peripheral region of the second conductivity type, the second conductivity type peripheral region connected to the body region, and
each of the inter-trench regions within the first element range including:
a first region of a first conductivity type in contact with the first metal layer and the gate insulating film, and
a body region of a second conductivity type in contact with the first metal layer and in contact with the gate insulating film below the first region,

a gate insulating film covering inner surfaces of the first trenches and inner surfaces of the second trenches;
a gate electrode disposed across inner portions of the first trenches and inner portions of the second trenches, the gate electrode insulated from the semiconductor substrate by the gate insulating film;
an interlayer insulating film covering the upper surface and the gate electrode range across the first element range and the inactive region, within the first element range, a contact hole is provided in a portion of the interlayer insulation film that covers the upper surface within the inactive region, and a contact hole is not provided in the portion of the interlayer insulation film that covers the upper surface;
a first metal layer covering the interlayer insulating film and insulated from the gate electrode by the interlayer insulating film, the first metal layer in contact with the semiconductor substrate within the contact hole, a recess is provided on a surface of the first metal layer above the contact hole;
an insulating protective film covering a portion of the first metal layer on an outer peripheral side in the inactive region, an opening is provided in the insulating protective film in a range wider than the first element range and a side surface of the opening disposed in the inactive region;
a second metal layer in contact with the surface of the first metal layer in the opening and additionally in contact with the side surface of the opening, the second metal layer having a linear expansion coefficient smaller than a linear expansion coefficient of the first metal layer; and
a second region of the first conductivity type of the semiconductor substrate disposed across below the body region and below the second conductivity type peripheral region, the second region in contact with the gate insulating film below the body region and separated from the first regions by the body region.

2. The switching device of claim 1 , wherein a lower end of the second conductivity type peripheral region is positioned below a lower end of each of the first trenches within the inactive region.

3. The switching device of claim 2 , wherein a second conductivity-type impurity density of the second conductivity-type peripheral region is higher than a second conductivity-type impurity density of a portion of the body region positioned below the first region.

4. The switching device of claim 1 , wherein
the semiconductor substrate includes an outer peripheral voltage resistant range disposed between the inactive region and the outer peripheral end surface of the semiconductor substrate, and
a guard ring of the second conductivity type is provided in the outer peripheral voltage resistant range, the guard ring exposed on the upper surface, surrounding the first element range and the inactive region, and electrically separated from the first metal layer.

5. The switching device of claim 4 , wherein:
the semiconductor substrate further includes a second element range disposed between inactive region and the outer peripheral voltage resistant range;
the first trenches extend across the first element range, the inactive region, and the second element range;
within the second element range, a plurality of the second trenches is provided in the upper surface in each of the inter-trench regions and a contact hole is provided in a portion of the interlayer insulation film that covers the upper surface;
the first metal layer is in contact with the upper surface in the contact hole within the second element range;
the insulating protective film covers the first metal layer in the second element range;
the second metal layer is disposed across from on the first metal in the opening and to on the insulating protective film;
an outer peripheral side end portion of the second metal layer is positioned on an inner peripheral side relative to an outer peripheral side end portion of the first metal layer; and
each of the inter-trench regions in the second element range includes the first region and the body region.

Assignees

• Toyota Motor Co Ltd

Inventors

• Soeno Akitaka
• Kuno Takashi

Classifications

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/59

  Bond pads specially adapted therefor · CPC title

• H10W42/00

  Arrangements for protection of devices (arrangements for thermal protection H10W40/00) · CPC title