Thin film transistor, display substrate and display device

Patent metadata

Field	Value
Publication number	US-12477777-B2
Application number	US-202218021778-A
Country	US
Kind code	B2
Filing date	Mar 31, 2022
Priority date	Mar 31, 2022
Publication date	Nov 18, 2025
Grant date	Nov 18, 2025

Abstract

Provided are a thin film transistor, a display substrate and a display device, the thin film transistor includes: a gate on a base substrate; an active layer between the gate and the base substrate, the active layer includes a source contact portion, a drain contact portion and a middle portion therebetween, orthographic projections of the middle portion and the gate on the base substrate overlaps to form a first overlapping region, a material of the middle portion includes a metal oxide containing a doped element, a dissociation energy of the doped element from an oxygen element is greater than 500 Kj/mol; a source connected to the source contact portion and a drain connected to the drain contact portion, a ratio of an area of the orthographic projection of the gate on the base substrate to an area of the first overlapping region is less than or equal to 3.

First claim

What is claimed is:

1 . A thin film transistor, comprising:
a gate disposed on a base substrate; an active layer located between the gate and the base substrate and insulated and spaced from the gate, where the active layer comprises a source contact portion, a drain contact portion and a middle portion located between the source contact portion and the drain contact portion, and an orthographic projection of the middle portion on the base substrate is overlapped with an orthographic projection of the gate on the base substrate to form a first overlapping region, a material of the middle portion comprises a metal oxide containing a doped element, and a dissociation energy of the doped element from an oxygen element is greater than 500 Kj/mol; and a source and a drain, the source being electrically connected to the source contact portion, the drain being electrically connected to the drain contact portion, wherein a ratio of an area of the orthographic projection of the gate on the base substrate to an area of the first overlapping region is less than or equal to 3.

2 . The thin film transistor of claim 1 , wherein the doped element comprises at least one of a rare earth element, a tungsten element, or a tantalum element.

3 . The thin film transistor of claim 1 , wherein the orthographic projection of the middle portion on the base substrate is a first projection, the gate comprises a plurality of first sides connected successively, an orthographic projection of at least one of the first sides on the base substrate is located outside the first projection, and a distance between the orthographic projection of the at least one of the first sides on the base substrate and the first projection is less than or equal to ¼ of a distance between the source contact portion and the drain contact portion.

4 . The thin film transistor of claim 3 , wherein a distance from the at least one of the first sides, whose orthographic projection on the base substrate is located outside the first projection, to the first projection is less than or equal to 1.5 μm.

5 . The thin film transistor of claim 3 , wherein an orthographic projection of each of the plurality of first sides on the base substrate is located outside the first projection.

6 . The thin film transistor of claim 1 , wherein a part of the orthographic projection of the middle portion on the base substrate exceeds the orthographic projection of the gate on the base substrate.

7 . A display substrate, comprising the thin film transistor of claim 1 .

8 . The display substrate of claim 7 , further comprising: a plurality of first signal lines and a plurality of second signal lines, wherein the first signal lines and the second signal lines are intersected to define a plurality of pixel regions, each pixel region is provided with a thin film transistor therein, the gate of each thin film transistor is connected with one of the first signal lines, and the source of each thin film transistor is connected with one of the second signal lines.

9 . The display substrate of claim 8 , wherein the first signal lines each extend in a first direction, and for at least one thin film transistor, the source contact portion and the drain contact portion are arranged along the first direction, a protrusion serving as the gate of the thin film transistor is formed on a side of the first signal line along a second direction, and the first direction intersects the second direction.

10 . The display substrate of claim 8 , wherein for at least one thin film transistor, a portion of the first signal line connected to the thin film transistor is provided opposite to the active layer of the thin film transistor, and the portion of the first signal line opposite to the active layer serves as the gate of the thin film transistor.

11 . The display substrate of claim 10 , wherein the first signal lines each extend in a first direction, and for at least one thin film transistor, the source contact portion and the drain contact portion are arranged along the first direction, and an orthographic projection of the first signal line connected to the thin film transistor on the base substrate passes through the orthographic projection of the middle portion on the base substrate.

12 . The display substrate of claim 10 , wherein the first signal lines each extend in a first direction, and for at least one thin film transistor, the source contact portion and the drain contact portion are arranged along a second direction, an orthographic projection of the first signal line connected to the thin film transistor on the base substrate passes through the orthographic projection of the middle portion on the base substrate, and the first direction intersects the second direction.

13 . A display device, comprising the display substrate of claim 7 .

14 . The thin film transistor of claim 2 , wherein the orthographic projection of the middle portion on the base substrate is a first projection, the gate comprises a plurality of first sides connected successively, an orthographic projection of at least one of the first sides on the base substrate is located outside the first projection, and a distance between the orthographic projection of the at least one of the first sides on the base substrate and the first projection is less than or equal to ¼ of a distance between the source contact portion and the drain contact portion.

15 . The thin film transistor of claim 14 , wherein a distance from the at least one of the first sides, whose orthographic projection on the base substrate is located outside the first projection, to the first projection is less than or equal to 1.5 μm.

16 . The thin film transistor of claim 15 , wherein an orthographic projection of each of the plurality of first sides on the base substrate is located outside the first projection.

17 . The thin film transistor of claim 2 , wherein a part of the orthographic projection of the middle portion on the base substrate exceeds the orthographic projection of the gate on the base substrate.

18 . A display device, comprising the display substrate of claim 8 .

19 . A display device, comprising the display substrate of claim 9 .

20 . A display device, comprising the display substrate of claim 10 .

Assignees

• Boe Technology Group Co Ltd
• Beijing Boe Technology Dev Co Ltd

Inventors

• Huang Jie
• Ning ce
• Li Zhengliang
• Hu hehe
• Yao Niangi
• Zhao Kun
• Li Feifei

Classifications

• H10P10/00

  Bonding of wafers, substrates or parts of devices · CPC title

• H10D30/673

  characterised by the shapes, relative sizes or dispositions of the gate electrodes · CPC title

• H10D30/6755

  Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title

• H10D30/67

  Thin-film transistors [TFT] {(Stacked nanowire, nanosheet or nanoribbon FETs H10D30/501)} · CPC title

• H10D64/27

  Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates · CPC title